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author | Alexandre Courbot <acourbot@nvidia.com> | 2025-08-21 13:49:32 +0900 |
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committer | Danilo Krummrich <dakr@kernel.org> | 2025-08-22 02:47:43 +0200 |
commit | 99e7f8e83a9c5a56ca20c4948b6126248c82c67d (patch) | |
tree | 6687cada636c83e4beeaa7b9a4d411f1970486c9 /rust/kernel/alloc/allocator/iter.rs | |
parent | d234f3aef5928c2f0d692cf43768ecced0abd672 (diff) |
gpu: nova-core: falcon: align DMA transfers to 256 bytes
Falcon DMA transfers are done in 256 bytes increments, and the method
responsible for initiating the transfer checked that the required length
was indeed a multiple of 256. While correct, this also requires callers
to specifically account for this limitation of DMA transfers, and we had
for instance the fwsec code performing a seemingly arbitrary (and
potentially overflowing) upwards alignment of the DMEM load size to
match this requirement.
Let's move that alignment into the loading code itself instead: since it
is working in terms of number of transfers, we can turn this upwards
alignment into a non-overflowing operation, and check that the requested
transfer remains into the limits of the DMA object. This also allows us
to remove a DMA-specific constant in the fwsec code.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Link: https://lore.kernel.org/r/20250821-falcondma_256b-v2-1-83e8647a24b5@nvidia.com
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
Diffstat (limited to 'rust/kernel/alloc/allocator/iter.rs')
0 files changed, 0 insertions, 0 deletions