summaryrefslogtreecommitdiff
path: root/rust/kernel/bits.rs
diff options
context:
space:
mode:
authorYanteng Si <siyanteng@cqsoftware.com.cn>2025-08-03 22:49:47 +0800
committerHuacai Chen <chenhuacai@loongson.cn>2025-08-03 22:49:47 +0800
commit41fee4f0036734bec427659f749e44cfe1821565 (patch)
treeb8c4d694afa2944aafd9b56a7e7e3d333758d36e /rust/kernel/bits.rs
parent0a91336e287ca2557fead5221d2c79e0effd034e (diff)
LoongArch: Complete KSave registers definition
According to the "LoongArch Reference Manual Volume 1: Basic Architecture", the KSave registers (SAVE0-SAVE15) are defined in Section 7.4.16 "Data Save (SAVE)" and listed in Table 7-1 "Control and Status Registers Overview". These registers occupy the CSR addresses from 0x30 to 0x3F, with 16 registers in total. This patch completes the definitions of KS9 to KS15, so as to match the architecture specification. Reviewed-by: Wentao Guan <guanwentao@uniontech.com> Signed-off-by: Yanteng Si <siyanteng@cqsoftware.com.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'rust/kernel/bits.rs')
0 files changed, 0 insertions, 0 deletions