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authorBrett Creeley <brett.creeley@amd.com>2023-12-04 13:09:36 -0800
committerJakub Kicinski <kuba@kernel.org>2023-12-05 20:49:51 -0800
commit5858036ca05658051ec61551e6699cca9c7d3369 (patch)
tree675d626554586dab6b1a452826730dbf43fb5880 /scripts/gdb/linux/interrupts.py
parentab807e9183425ddf6dd85ca622a51fe4cad2c577 (diff)
ionic: Re-arrange ionic_intr_info struct for cache perf
dim_coal_hw is accessed in the hotpath along with other values from the first cacheline of ionic_intr_info. So, re-arrange the structure so the hot path variables are on the first cacheline. Before: struct ionic_intr_info { char name[32]; /* 0 32 */ unsigned int index; /* 32 4 */ unsigned int vector; /* 36 4 */ u64 rearm_count; /* 40 8 */ unsigned int cpu; /* 48 4 */ /* XXX 4 bytes hole, try to pack */ cpumask_t affinity_mask; /* 56 1024 */ /* --- cacheline 16 boundary (1024 bytes) was 56 bytes ago --- */ u32 dim_coal_hw; /* 1080 4 */ /* size: 1088, cachelines: 17, members: 7 */ /* sum members: 1080, holes: 1, sum holes: 4 */ /* padding: 4 */ }; After: struct ionic_intr_info { char name[32]; /* 0 32 */ u64 rearm_count; /* 32 8 */ unsigned int index; /* 40 4 */ unsigned int vector; /* 44 4 */ unsigned int cpu; /* 48 4 */ u32 dim_coal_hw; /* 52 4 */ cpumask_t affinity_mask; /* 56 1024 */ /* size: 1080, cachelines: 17, members: 7 */ /* last cacheline: 56 bytes */ }; Signed-off-by: Brett Creeley <brett.creeley@amd.com> Signed-off-by: Shannon Nelson <shannon.nelson@amd.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Rahul Rameshbabu <rrameshbabu@nvidia.com> Link: https://lore.kernel.org/r/20231204210936.16587-6-shannon.nelson@amd.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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