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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-25 11:45:26 +0100 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@kernel.org> | 2025-07-24 00:37:59 +0200 |
| commit | 529a3ff283e7e788dd23d372aaf0820dac5822ae (patch) | |
| tree | e0d4e0208d690d21b77c80bea7da148c83538c00 /scripts/gdb/linux/mm.py | |
| parent | 832b2f3e3986c8ea8c24a7823ca5189746644bc4 (diff) | |
i2c: riic: Add support for RZ/T2H SoC
Add support for the Renesas RZ/T2H (R9A09G077) SoC, which features a
different interrupt layout for the RIIC controller. Unlike other SoCs
with individual error interrupts, RZ/T2H uses a combined error interrupt
(EEI).
Introduce a new IRQ descriptor table for RZ/T2H, along with a custom
ISR (`riic_eei_isr`) to handle STOP and NACK detection from the shared
interrupt.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # on RZ/A1
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250625104526.101004-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Diffstat (limited to 'scripts/gdb/linux/mm.py')
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