summaryrefslogtreecommitdiff
path: root/scripts/gdb/linux/proc.py
diff options
context:
space:
mode:
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2025-06-25 11:45:23 +0100
committerAndi Shyti <andi.shyti@kernel.org>2025-07-24 00:37:59 +0200
commit13aa792c10ada4f8870da5ba0fb51e478eb5a45e (patch)
treede2f07c11d0aae7f9a55e3adb65e5d75de39aada /scripts/gdb/linux/proc.py
parentbe221173ee918dff2adaf0e23b03aeea44902d5e (diff)
dt-bindings: i2c: renesas,riic: Document RZ/T2H and RZ/N2H support
Document support for the I2C Bus Interface (RIIC) found on the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The RIIC IP on these parts is similar to that on RZ/V2H(P) but supports only four interrupts (including a combined error/event), lacks FM+ mode, and does not require reset. Introduce a new compatible string `renesas,riic-r9a09g077` for RZ/T2H and use it as a fallback for RZ/N2H. Unlike earlier SoCs that use eight distinct interrupts, the RZ/T2H uses only four. Update the binding schema to reflect this interrupt layout and skip the `resets` property check, as it is not required on these SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20250625104526.101004-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Diffstat (limited to 'scripts/gdb/linux/proc.py')
0 files changed, 0 insertions, 0 deletions