diff options
| author | Qiang Yu <qiang.yu@oss.qualcomm.com> | 2025-07-22 17:11:51 +0800 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-08-11 16:43:07 -0500 |
| commit | df758a868dbc90cae98044d52a9d753575f50cfa (patch) | |
| tree | 6d42f4fe102ef0ea970b4f65e4006eca0589d562 /scripts/gdb/linux/radixtree.py | |
| parent | 6facfaff0fe3b4d5903bed6164eb5e60ee6cdb8f (diff) | |
arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP
Add perst, wake and clkreq sideband signals and required regulators in
PCIe3 controller and PHY device tree node. Describe the voltage rails of
the x8 PCI slots for PCIe3 port.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722091151.1423332-4-quic_wenbyao@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/radixtree.py')
0 files changed, 0 insertions, 0 deletions