diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2025-08-29 11:09:21 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-09-17 08:53:24 -0700 |
| commit | 02edab6ceefaaf8cb917e864d8c26dbac0ea9686 (patch) | |
| tree | 1045040ad6017c371c6ea90ec235ee674e0f6b6f /scripts/gdb/linux/timerlist.py | |
| parent | 8330671c57c7056ef5e1e8dccfcdda7d5fe6d0b0 (diff) | |
cxl: Add a cached copy of target_map to cxl_decoder
Add a cached copy of the hardware port-id list that is available at init
before all @dport objects have been instantiated. Change is in preparation
of delayed dport instantiation.
Reviewed-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Tested-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'scripts/gdb/linux/timerlist.py')
0 files changed, 0 insertions, 0 deletions