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| author | Chen Wang <unicorn_wang@outlook.com> | 2025-09-12 10:36:31 +0800 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2025-09-19 23:52:27 +0530 |
| commit | 1c72774df028429836eec3394212f2921bb830fc (patch) | |
| tree | 39192a30b2962fe5a3a2cde327025a5ad97b2979 /scripts/generate_rust_analyzer.py | |
| parent | 49a6c160ad4812476f8ae1a8f4ed6d15adfa6c09 (diff) | |
PCI: sg2042: Add Sophgo SG2042 PCIe driver
Add support for PCIe controller in Sophgo SG2042 SoC. The controller uses
the Cadence PCIe core programmed by pcie-cadence* common driver. The PCIe
controller in SG2042 works in host mode only, supporting data rate up to 16
GT/s and lanes up to x16 or x8.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
[mani: reworded description and minor code cleanups]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions