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| author | Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> | 2025-09-23 16:56:53 +0530 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2025-09-25 18:33:56 +0530 |
| commit | 4660e50cf81800f82eeecf743ad1e3e97ab72190 (patch) | |
| tree | 5d265636077d7e1f0d23b974f221ad776ec569e8 /scripts/generate_rust_analyzer.py | |
| parent | f6fd357f7afbeb34a633e5688a23b9d7eb49d558 (diff) | |
PCI: qcom: Prepare for the DWC ECAM enablement
To support the DWC ECAM mechanism, prepare the driver by performing below
configurations:
1. Since the ELBI region will be covered by the ECAM 'config' space,
override the 'elbi_base' with the address derived from 'dbi_base' and
the offset from PARF_SLV_DBI_ELBI register.
2. Block the transactions from the host bridge to devices other than Root
Port on the root bus to return all F's. This is required when the 'CFG
Shift Feature' of iATU is enabled.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
[mani: code split, reworded subject/description and comments]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20250923-controller-dwc-ecam-v10-3-e84390ba75fa@kernel.org
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions