diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:21 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:21 -0500 |
| commit | 86a3f3db9a0f4f5b9a6f77a63d063b57c146306b (patch) | |
| tree | 5469093b8af8fdd1896891fce70cffa4d96a6e22 /scripts/generate_rust_analyzer.py | |
| parent | 531abff0fa53bc3a2f7f69b2693386eb6bda96e5 (diff) | |
| parent | 2bdf1d428f48e1077791bb7f88fd00262118256d (diff) | |
Merge branch 'pci/controller/rcar-gen4'
- Fix a typo that prevented correct PHY initialization (Marek Vasut)
- Add a missing 1ms delay after PWR reset assertion as required by the V4H
manual (Marek Vasut)
- Assure reset has completed before DBI access to avoid SError (Marek
Vasut)
- Fix inverted PHY initialization check, which sometimes led to timeouts
and failure to start the controller (Marek Vasut)
* pci/controller/rcar-gen4:
PCI: rcar-gen4: Fix inverted break condition in PHY initialization
PCI: rcar-gen4: Assure reset occurs before DBI access
PCI: rcar-gen4: Add missing 1ms delay after PWR reset assertion
PCI: rcar-gen4: Fix PHY initialization
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions