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| author | Qiang Yu <qiang.yu@oss.qualcomm.com> | 2025-09-19 19:53:25 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-09-26 16:14:21 -0500 |
| commit | 96a17ed17b369109b662b40345df961b412c1cd3 (patch) | |
| tree | c13be7a416b138deb4dd6f171243c2bd4ab2010a /scripts/generate_rust_analyzer.py | |
| parent | 57a48a2619c5f99d48748f9c34db510efe5ee7c9 (diff) | |
dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller
On the Qualcomm Glymur platform, the fifth PCIe host is compatible with
the DWC controller present on the X1E80100 platform, but does not have
cnoc_sf_axi clock. Hence, set minItems of clocks and clock-names to six.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250919142325.1090059-1-pankaj.patil@oss.qualcomm.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions