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| author | Li Ming <ming.li@zohomail.com> | 2025-07-11 11:23:56 +0800 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-07-11 09:46:53 -0700 |
| commit | 03ff65c02559e8da32be231d7f10fe899233ceae (patch) | |
| tree | a46c0f2e44919cdea6be53befba36c9751aeb0ae /scripts/lib/kdoc/kdoc_output.py | |
| parent | 5b6031c832c2747d58d3f0130098d965ef050b9a (diff) | |
cxl/edac: Fix wrong dpa checking for PPR operation
Per Table 8-143. "Get Partition Info Output Payload" in CXL r3.2 section
8.2.10.9.2.1 "Get Partition Info(Opcode 4100h)", DPA 0 is a valid
address of a CXL device. However, cxl_do_ppr() considers it as an
invalid address, so that user will get an -EINVAL when user calls the
sysfs interface of the edac driver to trigger a Post Package Repair(PPR)
operation for DPA 0 on a CXL device. The correct implementation should
be checking if the input DPA is in the DPA range of the CXL device.
Fixes: be9b359e056a ("cxl/edac: Add CXL memory device soft PPR control feature")
Signed-off-by: Li Ming <ming.li@zohomail.com>
Tested-by: Shiju Jose <shiju.jose@huawei.com>
Reviewed-by: Shiju Jose <shiju.jose@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20250711032357.127355-3-ming.li@zohomail.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'scripts/lib/kdoc/kdoc_output.py')
0 files changed, 0 insertions, 0 deletions