diff options
| author | Rob Herring (Arm) <robh@kernel.org> | 2025-06-09 16:54:57 -0500 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-07-03 16:29:28 +0200 |
| commit | f060fee24a52d6d9d6c0d963c24da7f2b42a3d5d (patch) | |
| tree | abdd1cfc4ef07ba693b859dbca1353cacee73133 /scripts/lib/kdoc/kdoc_output.py | |
| parent | caec315724f086c734688bd44f4c3a7a19526731 (diff) | |
arm64: dts: lg: Add missing PL011 "uartclk"
The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
LG131x SoCs are missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Link: https://lore.kernel.org/r/20250609-dt-lg-fixes-v1-2-e210e797c2d7@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'scripts/lib/kdoc/kdoc_output.py')
0 files changed, 0 insertions, 0 deletions