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authorJani Nikula <jani.nikula@intel.com>2025-04-03 15:21:33 +0300
committerJani Nikula <jani.nikula@intel.com>2025-04-09 12:45:17 +0300
commitca677505e4776bd1abf90096f3eab3b68079dde9 (patch)
treeee0a2e103458bb6ccfe18b00f81f792af5c9bc61 /scripts/lib
parent8b6b67938ed5a0a4385c38efad91cb3e6f7e5765 (diff)
drm/i915/dsi: separate clock and data lane prepare timing
The history of why the max of VBT clock and data lane prepare timing parameter is used for both instead of each individually is unknown. Separate them to follow what the Windows driver does. Cc; William Tseng <william.tseng@intel.com> Reviewed-by: William Tseng <william.tseng@intel.com> Tested-by: William Tseng <william.tseng@intel.com> Link: https://lore.kernel.org/r/079a26d0aae79f299aee0397dad2d6519cd55071.1743682608.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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