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| author | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:23 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:23 -0500 |
| commit | c4c50d8da88c383cc446e60fda8c2c317ebb93e5 (patch) | |
| tree | 0ee3247e16d56b2140734be63eb80b772e560821 /tools/docs/parse-headers.py | |
| parent | 30eccd3b7d2f0cdd86929fc9a0f7d75493fb520e (diff) | |
| parent | e1bd928479fb1fa60e9034b0fdb1ab9f3fa92f33 (diff) | |
Merge branch 'pci/controller/tegra'
- Correct the devm_kcalloc() argument order (Alok Tiwari)
- When asserting PERST#, disable the controller instead of mistakenly
disabling the PLL twice (Nagarjuna Kristam)
- Convert struct tegra_msi mask_lock to raw spinlock to avoid a lock
nesting error (Marek Vasut)
- Rename 'root_bus' to 'root_port_bus' for clarity (Manivannan Sadhasivam)
* pci/controller/tegra:
PCI: tegra194: Rename 'root_bus' to 'root_port_bus' in tegra_pcie_downstream_dev_to_D0()
PCI: tegra: Convert struct tegra_msi mask_lock into raw spinlock
PCI: tegra194: Fix duplicate PLL disable in pex_ep_event_pex_rst_assert()
PCI: tegra: Fix devm_kcalloc() argument order for port->phys allocation
Diffstat (limited to 'tools/docs/parse-headers.py')
0 files changed, 0 insertions, 0 deletions