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| author | Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> | 2025-09-26 14:22:45 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-09-26 16:03:02 -0500 |
| commit | cef730075cfe2b2091e3c94471cc0a78405401d5 (patch) | |
| tree | 97857721015679f8e682f9b24dbfbcc44f520b5d /tools/docs/parse-headers.py | |
| parent | 8f5ae30d69d7543eee0d70083daf4de8fe15d585 (diff) | |
PCI: dwc: Support 16-lane operation
Some hosts support 16 lanes of PCIe. Make num-lanes accept that number.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250926-topic-pcie_16ln-v1-1-c249acc18790@oss.qualcomm.com
Diffstat (limited to 'tools/docs/parse-headers.py')
0 files changed, 0 insertions, 0 deletions