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| author | Haibo Chen <haibo.chen@nxp.com> | 2025-09-22 16:47:15 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2025-10-13 13:32:48 +0100 |
| commit | f43579ef3500527649b1c233be7cf633806353aa (patch) | |
| tree | 6507e38d244a1c3910567fef2abd250bcd170d9d /tools/docs/parse-headers.py | |
| parent | b93b4269791fdebbac2a9ad26f324dc2abb9e60f (diff) | |
spi: spi-nxp-fspi: limit the clock rate for different sample clock source selection
For different sample clock source selection, the max frequency
flexspi supported are different. For mode 0, max frequency is 66MHz.
For mode 3, the max frequency is 166MHz.
Refer to 3.9.9 FlexSPI timing parameters on page 65.
https://www.nxp.com/docs/en/data-sheet/IMX8MNCEC.pdf
Though flexspi maybe still work under higher frequency, but can't
guarantee the stability. IC suggest to add this limitation on all
SoCs which contain flexspi.
Fixes: c07f27032317 ("spi: spi-nxp-fspi: add the support for sample data from DQS pad")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20250922-fspi-fix-v1-3-ff4315359d31@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/docs/parse-headers.py')
0 files changed, 0 insertions, 0 deletions