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| author | Matthew Gerlach <matthew.gerlach@altera.com> | 2025-04-24 07:43:41 -0700 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-05-21 18:49:56 +0200 |
| commit | 24822c4b476c7d7387eec21711d7908a86728d8a (patch) | |
| tree | f9d609d0a6e45cdd2d0c3ccca0d858820344cd80 /tools/lib/python | |
| parent | 6c265faf1a409ccb9b99e8a90166a8836db6246f (diff) | |
dt-bindings: clock: socfpga: convert to yaml
Convert the clock device tree bindings to yaml for the Altera SoCFPGA
Cyclone5, Arria5, and Arria10 chip families. Since the clock nodes are
subnodes to Altera SOCFPGA Clock Manager, the yaml was added to
socfpga-clk-manager.yaml.
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions