clk: renesas: r9a09g077: Add PCLKL core clock

Add the Peripheral Module Clock L (PCLKL) for the RZ/T2H (R9A09G077)
SoC.  PCLKL is sourced from PLL1 and runs at 62.5MHz.  It is used by
various low-speed peripherals such as IIC and WDT.

Also update LAST_DT_CORE_CLK to reflect the addition of PCLKL, ensuring
correct enumeration of core clocks exposed to DT.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250617155757.149597-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

0 files changed, 0 insertions, 0 deletions