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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-05-28 14:25:58 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-10 10:32:35 +0200 |
| commit | e6b6e3e08f012f967bb0babf4b0da4535d7f617b (patch) | |
| tree | 6cde75eb0998fdc0c0bd19415578316f37e5bad7 /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | 705d9f8f180851c60e6a344881661c3d44b92313 (diff) | |
clk: renesas: r9a09g056: Add clock and reset entries for USB2.0
Add clock and reset entries for USB2.0.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250528132558.167178-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions