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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-25 15:17:03 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:24:10 +0200 |
| commit | 2a76193f7cc03de5b2745d069926ebc431dd5ba4 (patch) | |
| tree | 538c2c0270862cbd06667748bb59c69210c35c77 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 292bf6c5b8100ba4e16cd194bdc89785f6fb6f7a (diff) | |
dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
a core clock for the SDHI IP and operates at 800MHz.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions