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| author | Wesley Chalmers <Wesley.Chalmers@amd.com> | 2022-11-03 22:29:31 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-02-08 17:15:14 -0500 |
| commit | 4f1b5e739dfd1edde33329e3f376733a131fb1ff (patch) | |
| tree | 035acfde872cb311fb38a3605b5b97ace5ca298c /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 642f1b405255ec5574eb20a3f72e29676b94679c (diff) | |
drm/amd/display: Do not set DRR on pipe commit
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
[HOW]
Defer all DPP adjustment requests till optimized_required is false.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions