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| author | Paul Kocialkowski <paulk@sys-base.io> | 2025-07-04 17:40:07 +0200 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2025-07-14 11:51:14 +0800 |
| commit | e8ab346f9907a1a3aa2f0e5decf849925c06ae2e (patch) | |
| tree | 08e6af0c9a0c152a276fdca9ee1ea404367ed09d /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | c17b1b6c86059664e91008a23547ef0aadfc2228 (diff) | |
clk: sunxi-ng: v3s: Fix de clock definition
The de clock is marked with CLK_SET_RATE_PARENT, which is really not
necessary (as confirmed from experimentation) and significantly
restricts flexibility for other clocks using the same parent.
In addition the source selection (parent) field is marked as using
2 bits, when it the documentation reports that it uses 3.
Fix both issues in the de clock definition.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Link: https://patch.msgid.link/20250704154008.3463257-1-paulk@sys-base.io
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions