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| author | Krzysztof Adamski <k@japko.eu> | 2016-02-22 14:03:26 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-02-25 11:33:05 -0800 |
| commit | 097872945ea6b70707772eea520c4e273a9c7321 (patch) | |
| tree | d0689a2f2b0d0ef491d85070d2039ec18b19952f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | f9ca30440c0866a1cb0ecb68604fdad3a108f9fb (diff) | |
dts: sun8i-h3: Add APB0 related clocks and resets
APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exists and works, though. There are probably other gates
there but I don't know their order right now and I don't have access to
their peripherals on my board to test them.
After some experiments and reviewing how this is organized on other
sunxi SoCs, I couldn't actually find any way to disable clocks for R_PIO
and they are working properly without doing anything so I assume they
are connected straight to the 24Mhz oscillator for now.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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