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| author | Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> | 2025-04-15 09:53:42 +0000 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-06-17 21:59:42 -0500 |
| commit | 6531b4b095dacc3067c91a802e1518f3faad72b4 (patch) | |
| tree | c149ee1853c040322cb090280b1e971fecc2867a /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 66bf410e72348691cfbc222afae4414ed1cc657c (diff) | |
arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P
SoCs. L3 instances on this SoC are same as SM8250 and SC7280 SoCs.
These SoCs use EPSS_L3_PERF register instead of REG_L3_VOTE register for
programming the perf level. This is taken care in the data associated
with the target specific compatible. Since, the HW is same in the all
SoCs with EPSS support, using the same generic compatible for all.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Link: https://lore.kernel.org/r/20250415095343.32125-7-quic_rlaggysh@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions