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| author | Ben Zong-You Xie <ben717@andestech.com> | 2025-07-11 21:30:17 +0800 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-07-21 16:51:52 +0200 |
| commit | 00dba19aa005c8cff5694adeea996b0ce85808cf (patch) | |
| tree | 7bba6d6309326185153c21548e444790b08de3c1 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 86731a2a651e58953fc949573895f2fa6d456841 (diff) | |
riscv: add Andes SoC family Kconfig support
The first SoC in the Andes series is QiLai. It includes a high-performance
quad-core RISC-V AX45MP cluster and one NX27V vector processor.
For further information, refer to [1].
[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-2-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions