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| author | José Roberto de Souza <jose.souza@intel.com> | 2022-11-21 11:24:49 +0200 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2022-11-22 06:02:29 -0800 |
| commit | ba51925da4ef763d6a3aa03b15241a85cdb76865 (patch) | |
| tree | f42155d8c40c40e9bc67a6db4a208868f3f99d17 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 529d95a6067b74da9d4d5d9ab3009b35c98c5fce (diff) | |
drm/i915/gsc: Only initialize GSC in tile 0
For multi-tile setups the GSC operational only on the tile 0.
Skip GSC auxiliary device creation for all other tiles
in GSC device init code.
Initialize basic GSC fields and use the same path
as HECI1 (HECI_PXP) device disable.
Cc: Tomas Winkler <tomas.winkler@intel.com>
Cc: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Acked-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221121092449.328674-1-alexander.usyskin@intel.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions