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| author | Ben Zong-You Xie <ben717@andestech.com> | 2025-07-11 21:30:20 +0800 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-07-21 16:51:52 +0200 |
| commit | 1f5ff8c363cf81e1b268108d1ed93b59b6a504f8 (patch) | |
| tree | 7b00ab3db849ee7645c548498b24fc0df99ee721 /tools/perf/scripts/python/parallel-perf.py | |
| parent | 6eeee4fb1930a3863911cf3b620ec340c9227952 (diff) | |
dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller
Add the DT binding documentation for Andes machine-level software
interrupt controller.
In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
second time with all interrupt sources tied to zero as the software
interrupt controller (PLICSW). PLICSW can generate machine-level software
interrupts through programming its registers.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-5-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions