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| author | José Roberto de Souza <jose.souza@intel.com> | 2018-06-26 13:16:44 -0700 |
|---|---|---|
| committer | Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> | 2018-06-26 17:15:55 -0700 |
| commit | 00c8f19463ab42d22332fc9c9fca605f12eadeb7 (patch) | |
| tree | a8af6c5be0df824eab1191a8eaf413e6aa1e56d2 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 3ebe3df50bb1db45c7bf1ce90c3d61c4eed1ba84 (diff) | |
drm/i915/psr: Enable CRC check in the static frame on the sink side
Sink can be configured to calculate the CRC over the static frame and
compare with the CRC calculated and transmited in the VSC SDP by
source, if there is a mismatch sink will do a short pulse in HPD
and set DP_PSR_LINK_CRC_ERROR in DP_PSR_ERROR_STATUS.
Spec: 7723
v6:
andling DP_PSR_LINK_CRC_ERROR here and remove "bdw+" from commit
message
v4:
patch moved to after 'drm/i915/psr: Avoid PSR exit max time timeout'
to avoid touch in 2 patches EDP_PSR_DEBUG.
v3:
disabling PSR instead of exiting on error
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180626201644.21932-5-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions