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authorJagadeesh Kona <quic_jkona@quicinc.com>2025-04-15 09:53:43 +0000
committerBjorn Andersson <andersson@kernel.org>2025-06-17 21:59:42 -0500
commit985237d49c4cf0254810b4b8078d240ba9bfc2ec (patch)
treebe218dd624257b6e14d26f455f004656210db574 /tools/perf/scripts/python/task-analyzer.py
parent6531b4b095dacc3067c91a802e1518f3faad72b4 (diff)
arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
Add OPP tables required to scale DDR and L3 per freq-domain on SA8775P platform. If a single OPP table is used for both CPU domains, then _allocate_opp_table() won't be invoked for CPU4 but instead CPU4 will be added as device under the CPU0 OPP table. Due to this, dev_pm_opp_of_find_icc_paths() won't be invoked for CPU4 device and hence CPU4 won't be able to independently scale it's interconnects. Both CPU0 and CPU4 devices will scale the same ICC path which can lead to one device overwriting the BW vote placed by other device. Hence CPU0 and CPU4 require separate OPP tables to allow independent scaling of DDR and L3 frequencies for each CPU domain, with the final DDR and L3 frequencies being an aggregate of both. Co-developed-by: Shivnandan Kumar <quic_kshivnan@quicinc.com> Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415095343.32125-8-quic_rlaggysh@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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