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| author | Andy Yan <andy.yan@rock-chips.com> | 2025-06-15 20:39:05 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-07-10 13:47:36 +0200 |
| commit | 132b62280a9dbe38c627183ae7f1611de3ee0d9a (patch) | |
| tree | 1e97ced4455cc0ee0b79556da6087d2979a0a23a /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | 19272b37aa4f83ca52bdf9c16d5d81bdd1354494 (diff) | |
clk: rockchip: rk3568: Add PLL rate for 132MHz
Add PLL rate for 132 MHz to allow raydium-rm67200 panel with
1080x1920 resolution to run at 60 fps that driven by VPLL.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20250615123922.661998-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions