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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-05-13 16:46:32 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-10 10:20:45 +0200 |
| commit | 82a0bc727cc2abd5fa6c4e63f0c303a9244a8ca0 (patch) | |
| tree | a9b10e2a7d8b866222814a1eab7ff6197ce66d27 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | bfb0bc6bdfdaa58abeec4c99e9b2cd25e550306d (diff) | |
clk: renesas: r9a09g056-cpg: Add clock and reset entries for OSTM instances
Introduce a new fixed divider .pllcln_div16 which is sourced from PLLCLN
and add PCLK module clocks gtm_0_pclk through gtm_7_pclk for OSTM0-7.
Add corresponding reset lines GTM_0_PRESETZ through GTM_7_PRESETZ to
control the OSTM instances.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions