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authorBjorn Helgaas <bhelgaas@google.com>2025-07-31 16:12:05 -0500
committerBjorn Helgaas <bhelgaas@google.com>2025-07-31 16:12:05 -0500
commitdc6061ed6becae8baabc5c6fd1c4cbf1f8ffa41f (patch)
tree20227b13fc20f3c1c91e5b8f2e6a45d0251977bb /tools/perf/util/scripting-engines/trace-event-python.c
parent480b315376eeabbcd206e41df7e7c1e9ed8d71b9 (diff)
parente8e7c1e95d6d4ccdc53654a5966d2183532ab115 (diff)
Merge branch 'pci/controller/brcmstb'
- Add optional DT 'num-lanes' property and if present, use it to override the Maximum Link Width advertised in Link Capabilities (Jim Quinlan) * pci/controller/brcmstb: PCI: brcmstb: Replace open coded value with PCIE_T_RRS_READY_MS MAINTAINERS: Drop Nicolas from maintaining pcie-brcmstb PCI: brcmstb: Set MLW based on "num-lanes" DT property if present dt-bindings: PCI: brcm,stb-pcie: Add num-lanes property
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