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| author | John Madieu <john.madieu.xa@bp.renesas.com> | 2025-07-02 02:57:03 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-08 11:36:16 +0200 |
| commit | e6e54229f328c30a1b4ecba1253f9d314dd42e33 (patch) | |
| tree | 44cb40af39a0ba2cabc23fe5142d629316607f1a /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | fc7dd515374455f07cdd24b8bad3c7952e812bff (diff) | |
clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
clocks needed by these two GBETH IPs.
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250702005706.1200059-2-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions