diff options
| -rw-r--r-- | arch/arm/boot/dts/exynos3250.dtsi | 11 | ||||
| -rw-r--r-- | arch/arm/boot/dts/exynos4210.dtsi | 11 | ||||
| -rw-r--r-- | arch/arm/boot/dts/exynos4412.dtsi | 17 | ||||
| -rw-r--r-- | arch/arm/boot/dts/exynos5250.dtsi | 11 | ||||
| -rw-r--r-- | arch/arm/boot/dts/exynos5260.dtsi | 38 | ||||
| -rw-r--r-- | arch/arm/boot/dts/exynos5420-cpus.dtsi | 32 | ||||
| -rw-r--r-- | arch/arm/boot/dts/exynos5422-cpus.dtsi | 32 |
7 files changed, 146 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 77ab7193b903..a10b789d8acf 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -50,6 +50,17 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 70baad9b11f0..7e7d65ce6585 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -32,6 +32,17 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + cpu0: cpu@900 { device_type = "cpu"; compatible = "arm,cortex-a9"; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index a142fe84010b..d3802046c8b8 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -35,6 +35,23 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + cpu0: cpu@a00 { device_type = "cpu"; compatible = "arm,cortex-a9"; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 2ea2caaca4e2..4ffa9253b566 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -50,6 +50,17 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 973448c4ad93..52fa211525ce 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -34,42 +34,68 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + core1 { + cpu = <&cpu3>; + }; + core2 { + cpu = <&cpu4>; + }; + core3 { + cpu = <&cpu5>; + }; + }; + }; + + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; cci-control-port = <&cci_control1>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; cci-control-port = <&cci_control1>; }; - cpu@100 { + cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; cci-control-port = <&cci_control0>; }; - cpu@101 { + cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; cci-control-port = <&cci_control0>; }; - cpu@102 { + cpu4: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; cci-control-port = <&cci_control0>; }; - cpu@103 { + cpu5: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x103>; diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index 58d1c54cf925..e9f4eb75b50f 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -22,6 +22,38 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index 4b641b9b8179..412a0bb4b988 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -21,6 +21,38 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + cpu0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a7"; |