diff options
| -rw-r--r-- | arch/arm/boot/dts/meson.dtsi | 37 | ||||
| -rw-r--r-- | arch/arm/boot/dts/meson6-atv1200.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/meson6.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/meson8.dtsi | 92 |
4 files changed, 132 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index e6539ea5a711..03bcff87bd27 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -50,6 +50,13 @@ / { interrupt-parent = <&gic>; + L2: l2-cache-controller@c4200000 { + compatible = "arm,pl310-cache"; + reg = <0xc4200000 0x1000>; + cache-unified; + cache-level = <2>; + }; + gic: interrupt-controller@c4301000 { compatible = "arm,cortex-a9-gic"; reg = <0xc4301000 0x1000>, @@ -106,5 +113,35 @@ clocks = <&clk81>; status = "disabled"; }; + + i2c_AO: i2c@c8100500 { + compatible = "amlogic,meson6-i2c"; + reg = <0xc8100500 0x20>; + interrupts = <0 92 1>; + clocks = <&clk81>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_A: i2c@c1108500 { + compatible = "amlogic,meson6-i2c"; + reg = <0xc1108500 0x20>; + interrupts = <0 21 1>; + clocks = <&clk81>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_B: i2c@c11087c0 { + compatible = "amlogic,meson6-i2c"; + reg = <0xc11087c0 0x20>; + interrupts = <0 128 1>; + clocks = <&clk81>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; /* end of / */ diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts index dc2541faf1ec..d7d351a68944 100644 --- a/arch/arm/boot/dts/meson6-atv1200.dts +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -50,7 +50,7 @@ / { model = "Geniatech ATV1200"; - compatible = "geniatech,atv1200"; + compatible = "geniatech,atv1200", "amlogic,meson6"; aliases { serial0 = &uart_AO; diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index 4ba49127779f..8b33be15af94 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -60,12 +60,14 @@ cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; reg = <0x200>; }; cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; reg = <0x201>; }; }; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi new file mode 100644 index 000000000000..1f442a7fe03b --- /dev/null +++ b/arch/arm/boot/dts/meson8.dtsi @@ -0,0 +1,92 @@ +/* + * Copyright 2014 Carlo Caione <carlo@caione.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "meson.dtsi" + +/ { + model = "Amlogic Meson8 SoC"; + compatible = "amlogic,meson8"; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x200>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x201>; + }; + + cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x202>; + }; + + cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x203>; + }; + }; + + clk81: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <141666666>; + }; +}; /* end of / */ |