diff options
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fbc.c | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
2 files changed, 15 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index e3934424040b..eeb97305e767 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -115,7 +115,7 @@ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915, * be 512 byte aligned. Aligning each line to 512 bytes guarantees * that regardless of the compression limit we choose later. */ - if (DISPLAY_VER(i915) == 9) + if (DISPLAY_VER(i915) >= 9) return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(cache)); else return stride; @@ -356,10 +356,18 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) const struct intel_fbc_reg_params *params = &fbc->params; u32 dpfc_ctl; - /* Display WA #0529: skl, kbl, bxt. */ - if (DISPLAY_VER(dev_priv) == 9) { + if (DISPLAY_VER(dev_priv) >= 10) { + u32 val = 0; + + if (params->override_cfb_stride) + val |= FBC_STRIDE_OVERRIDE | + FBC_STRIDE(params->override_cfb_stride / fbc->limit); + + intel_de_write(dev_priv, GLK_FBC_STRIDE, val); + } else if (DISPLAY_VER(dev_priv) == 9) { u32 val = 0; + /* Display WA #0529: skl, kbl, bxt. */ if (params->override_cfb_stride) val |= CHICKEN_FBC_STRIDE_OVERRIDE | CHICKEN_FBC_STRIDE(params->override_cfb_stride / fbc->limit); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 61d29068925c..24017d38c6f6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3360,6 +3360,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8) #define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14) #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23) +#define GLK_FBC_STRIDE _MMIO(0x43228) +#define FBC_STRIDE_OVERRIDE REG_BIT(15) +#define FBC_STRIDE_MASK REG_GENMASK(14, 0) +#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) #define ILK_FBC_RT_BASE _MMIO(0x2128) #define ILK_FBC_RT_VALID (1 << 0) #define SNB_FBC_FRONT_BUFFER (1 << 1) |