diff options
| -rw-r--r-- | arch/x86/kernel/cpu/mce/amd.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 117165c357b7..6d16b4589eef 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -308,6 +308,23 @@ static void smca_configure(unsigned int bank, unsigned int cpu) high |= BIT(5); } + /* + * SMCA Corrected Error Interrupt + * + * MCA_CONFIG[IntPresent] is bit 10, and tells us if the bank can + * send an MCA Thresholding interrupt without the OS initializing + * this feature. This can be used if the threshold limit is managed + * by the platform. + * + * MCA_CONFIG[IntEn] is bit 40 (8 in the high portion of the MSR). + * The OS should set this to inform the platform that the OS is ready + * to handle the MCA Thresholding interrupt. + */ + if ((low & BIT(10)) && data->thr_intr_en) { + __set_bit(bank, data->thr_intr_banks); + high |= BIT(8); + } + this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); wrmsr(smca_config, low, high); |