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-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml54
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml1
-rw-r--r--Documentation/devicetree/bindings/riscv/andes.yaml25
-rw-r--r--Documentation/devicetree/bindings/timer/andestech,plmt0.yaml53
-rw-r--r--MAINTAINERS9
-rw-r--r--arch/riscv/Kconfig.socs7
-rw-r--r--arch/riscv/boot/dts/Makefile1
-rw-r--r--arch/riscv/boot/dts/andes/Makefile2
-rw-r--r--arch/riscv/boot/dts/andes/qilai-voyager.dts28
-rw-r--r--arch/riscv/boot/dts/andes/qilai.dtsi186
-rw-r--r--arch/riscv/configs/defconfig1
11 files changed, 367 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
new file mode 100644
index 000000000000..eb2eb611ac09
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes machine-level software interrupt controller
+
+description:
+ In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
+ second time with all interrupt sources tied to zero as the software interrupt
+ controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
+ inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
+ controller is the parent interrupt controller for PLIC_SW. PLIC_SW can
+ generate machine-mode inter-processor interrupts through programming its
+ registers.
+
+maintainers:
+ - Ben Zong-You Xie <ben717@andestech.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - andestech,qilai-plicsw
+ - const: andestech,plicsw
+
+ reg:
+ maxItems: 1
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 15872
+ description:
+ Specifies which harts are connected to the PLIC_SW. Each item must points
+ to a riscv,cpu-intc node, which has a riscv cpu node as parent.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+
+examples:
+ - |
+ interrupt-controller@400000 {
+ compatible = "andestech,qilai-plicsw", "andestech,plicsw";
+ reg = <0x400000 0x400000>;
+ interrupts-extended = <&cpu0intc 3>,
+ <&cpu1intc 3>,
+ <&cpu2intc 3>,
+ <&cpu3intc 3>;
+ };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index ffc4768bad06..5b827bc24301 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -53,6 +53,7 @@ properties:
oneOf:
- items:
- enum:
+ - andestech,qilai-plic
- renesas,r9a07g043-plic
- const: andestech,nceplic100
- items:
diff --git a/Documentation/devicetree/bindings/riscv/andes.yaml b/Documentation/devicetree/bindings/riscv/andes.yaml
new file mode 100644
index 000000000000..aa1edf1fdec7
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/andes.yaml
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/andes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes SoC-based boards
+
+maintainers:
+ - Ben Zong-You Xie <ben717@andestech.com>
+
+description:
+ Andes SoC-based boards
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - andestech,voyager
+ - const: andestech,qilai
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
new file mode 100644
index 000000000000..90b612096004
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes machine-level timer
+
+description:
+ The Andes machine-level timer device (PLMT0) provides machine-level timer
+ functionality for a set of HARTs on a RISC-V platform. It has a single
+ fixed-frequency monotonic time counter (MTIME) register and a time compare
+ register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
+ generated if MTIME >= MTIMECMP.
+
+maintainers:
+ - Ben Zong-You Xie <ben717@andestech.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - andestech,qilai-plmt
+ - const: andestech,plmt0
+
+ reg:
+ maxItems: 1
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 32
+ description:
+ Specifies which harts are connected to the PLMT0. Each item must points
+ to a riscv,cpu-intc node, which has a riscv cpu node as parent. The
+ PLMT0 supports 1 hart up to 32 harts.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+
+examples:
+ - |
+ interrupt-controller@100000 {
+ compatible = "andestech,qilai-plmt", "andestech,plmt0";
+ reg = <0x100000 0x100000>;
+ interrupts-extended = <&cpu0intc 7>,
+ <&cpu1intc 7>,
+ <&cpu2intc 7>,
+ <&cpu3intc 7>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index f8bf112a3a58..7039b4680a68 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21293,6 +21293,15 @@ F: drivers/irqchip/irq-riscv-intc.c
F: include/linux/irqchip/riscv-aplic.h
F: include/linux/irqchip/riscv-imsic.h
+RISC-V ANDES SoC Support
+M: Ben Zong-You Xie <ben717@andestech.com>
+S: Maintained
+T: git: https://github.com/ben717-linux/linux
+F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
+F: Documentation/devicetree/bindings/riscv/andes.yaml
+F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
+F: arch/riscv/boot/dts/andes/
+
RISC-V ARCHITECTURE
M: Paul Walmsley <paul.walmsley@sifive.com>
M: Palmer Dabbelt <palmer@dabbelt.com>
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index a9c3d2f6debc..61ceae0aa27a 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,12 @@
menu "SoC selection"
+config ARCH_ANDES
+ bool "Andes SoCs"
+ depends on MMU && !XIP_KERNEL
+ select ERRATA_ANDES
+ help
+ This enables support for Andes SoC platform hardware.
+
config ARCH_MICROCHIP_POLARFIRE
def_bool ARCH_MICROCHIP
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 64a898da9aee..3b99e91efa25 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += allwinner
+subdir-y += andes
subdir-y += canaan
subdir-y += microchip
subdir-y += renesas
diff --git a/arch/riscv/boot/dts/andes/Makefile b/arch/riscv/boot/dts/andes/Makefile
new file mode 100644
index 000000000000..c545c668ef70
--- /dev/null
+++ b/arch/riscv/boot/dts/andes/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ANDES) += qilai-voyager.dtb
diff --git a/arch/riscv/boot/dts/andes/qilai-voyager.dts b/arch/riscv/boot/dts/andes/qilai-voyager.dts
new file mode 100644
index 000000000000..fa7d2b32a9b4
--- /dev/null
+++ b/arch/riscv/boot/dts/andes/qilai-voyager.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
+ */
+
+#include "qilai.dtsi"
+
+/ {
+ model = "Voyager";
+ compatible = "andestech,voyager", "andestech,qilai";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@400000000 {
+ device_type = "memory";
+ reg = <0x4 0x00000000 0x4 0x00000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
new file mode 100644
index 000000000000..de3de32f8c39
--- /dev/null
+++ b/arch/riscv/boot/dts/andes/qilai.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <62500000>;
+
+ cpu0: cpu@0 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "zicntr", "zicsr", "zifencei",
+ "zihpm", "xandespmu";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <100000000>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-line-size = <64>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <128>;
+ d-cache-line-size = <64>;
+ next-level-cache = <&l2_cache>;
+
+ cpu0_intc: interrupt-controller {
+ compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu1: cpu@1 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <1>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "zicntr", "zicsr", "zifencei",
+ "zihpm", "xandespmu";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <100000000>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-line-size = <64>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <128>;
+ d-cache-line-size = <64>;
+ next-level-cache = <&l2_cache>;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "andestech,cpu-intc",
+ "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu2: cpu@2 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <2>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "zicntr", "zicsr", "zifencei",
+ "zihpm", "xandespmu";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <100000000>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-line-size = <64>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <128>;
+ d-cache-line-size = <64>;
+ next-level-cache = <&l2_cache>;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "andestech,cpu-intc",
+ "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu3: cpu@3 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <3>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "zicntr", "zicsr", "zifencei",
+ "zihpm", "xandespmu";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <100000000>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-line-size = <64>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <128>;
+ d-cache-line-size = <64>;
+ next-level-cache = <&l2_cache>;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "andestech,cpu-intc",
+ "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ plmt: timer@100000 {
+ compatible = "andestech,qilai-plmt", "andestech,plmt0";
+ reg = <0x0 0x00100000 0x0 0x100000>;
+ interrupts-extended = <&cpu0_intc 7>,
+ <&cpu1_intc 7>,
+ <&cpu2_intc 7>,
+ <&cpu3_intc 7>;
+ };
+
+ l2_cache: cache-controller@200000 {
+ compatible = "andestech,qilai-ax45mp-cache",
+ "andestech,ax45mp-cache", "cache";
+ reg = <0x0 0x00200000 0x0 0x100000>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ cache-line-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <0x200000>;
+ cache-unified;
+ };
+
+ plic_sw: interrupt-controller@400000 {
+ compatible = "andestech,qilai-plicsw",
+ "andestech,plicsw";
+ reg = <0x0 0x00400000 0x0 0x400000>;
+ interrupts-extended = <&cpu0_intc 3>,
+ <&cpu1_intc 3>,
+ <&cpu2_intc 3>,
+ <&cpu3_intc 3>;
+ };
+
+ plic: interrupt-controller@2000000 {
+ compatible = "andestech,qilai-plic",
+ "andestech,nceplic100";
+ reg = <0x0 0x02000000 0x0 0x2000000>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>;
+ riscv,ndev = <71>;
+ };
+
+ uart0: serial@30300000 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0x0 0x30300000 0x0 0x100000>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <50000000>;
+ reg-offset = <32>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ no-loopback-test;
+ };
+ };
+};
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index fe8bd8afb418..12f5f6ec00fa 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -22,6 +22,7 @@ CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_PROFILING=y
+CONFIG_ARCH_ANDES=y
CONFIG_ARCH_MICROCHIP=y
CONFIG_ARCH_SIFIVE=y
CONFIG_ARCH_SOPHGO=y
generated by cgit (git 2.34.1) at 2026-01-03 13:21:07 +0000