summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/soc/rockchip
diff options
context:
space:
mode:
Diffstat (limited to 'Documentation/devicetree/bindings/soc/rockchip')
-rw-r--r--Documentation/devicetree/bindings/soc/rockchip/grf.yaml21
1 files changed, 16 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 8cbf5b6772dd..1ab0b092e2a5 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -179,10 +179,12 @@ allOf:
properties:
gpio:
type: object
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3328-grf-gpio
- $ref: /schemas/gpio/rockchip,rk3328-grf-gpio.yaml#
-
- unevaluatedProperties: false
+ additionalProperties: true
power-controller:
type: object
@@ -208,8 +210,8 @@ allOf:
pcie-phy:
type: object
- description:
- Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
+ $ref: /schemas/phy/rockchip,rk3399-pcie-phy.yaml#
+ unevaluatedProperties: false
patternProperties:
"^phy@[0-9a-f]+$":
@@ -333,6 +335,15 @@ examples:
#phy-cells = <0>;
};
+ pcie-phy {
+ compatible = "rockchip,rk3399-pcie-phy";
+ #phy-cells = <1>;
+ clocks = <&cru SCLK_PCIEPHY_REF>;
+ clock-names = "refclk";
+ resets = <&cru SRST_PCIEPHY>;
+ reset-names = "phy";
+ };
+
phy@f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x20>;