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Diffstat (limited to 'arch/arm64/boot/dts/exynos/exynos2200.dtsi')
-rw-r--r--arch/arm64/boot/dts/exynos/exynos2200.dtsi561
1 files changed, 561 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
new file mode 100644
index 000000000000..6b5ac02d010f
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung's Exynos 2200 SoC device tree source
+ *
+ * Copyright (c) 2025, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ */
+
+#include <dt-bindings/clock/samsung,exynos2200-cmu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "samsung,exynos2200";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_alive;
+ pinctrl1 = &pinctrl_cmgp;
+ pinctrl2 = &pinctrl_hsi1;
+ pinctrl3 = &pinctrl_ufs;
+ pinctrl4 = &pinctrl_hsi1ufs;
+ pinctrl5 = &pinctrl_peric0;
+ pinctrl6 = &pinctrl_peric1;
+ pinctrl7 = &pinctrl_peric2;
+ pinctrl8 = &pinctrl_vts;
+ };
+
+ xtcxo: clock-1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "oscclk";
+ };
+
+ ext_26m: clock-2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "ext-26m";
+ };
+
+ ext_200m: clock-3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "ext-200m";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a510";
+ reg = <0>;
+ capacity-dmips-mhz = <260>;
+ dynamic-power-coefficient = <189>;
+ enable-method = "psci";
+ cpu-idle-states = <&little_cpu_sleep>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a510";
+ reg = <0x100>;
+ capacity-dmips-mhz = <260>;
+ dynamic-power-coefficient = <189>;
+ enable-method = "psci";
+ cpu-idle-states = <&little_cpu_sleep>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a510";
+ reg = <0x200>;
+ capacity-dmips-mhz = <260>;
+ dynamic-power-coefficient = <189>;
+ enable-method = "psci";
+ cpu-idle-states = <&little_cpu_sleep>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a510";
+ reg = <0x300>;
+ capacity-dmips-mhz = <260>;
+ dynamic-power-coefficient = <189>;
+ enable-method = "psci";
+ cpu-idle-states = <&little_cpu_sleep>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a710";
+ reg = <0x400>;
+ capacity-dmips-mhz = <380>;
+ dynamic-power-coefficient = <560>;
+ enable-method = "psci";
+ cpu-idle-states = <&big_cpu_sleep>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a710";
+ reg = <0x500>;
+ capacity-dmips-mhz = <380>;
+ dynamic-power-coefficient = <560>;
+ enable-method = "psci";
+ cpu-idle-states = <&big_cpu_sleep>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a710";
+ reg = <0x600>;
+ capacity-dmips-mhz = <380>;
+ dynamic-power-coefficient = <560>;
+ enable-method = "psci";
+ cpu-idle-states = <&big_cpu_sleep>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-x2";
+ reg = <0x700>;
+ capacity-dmips-mhz = <488>;
+ dynamic-power-coefficient = <765>;
+ enable-method = "psci";
+ cpu-idle-states = <&prime_cpu_sleep>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ little_cpu_sleep: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "c2";
+ entry-latency-us = <70>;
+ exit-latency-us = <170>;
+ min-residency-us = <2000>;
+ arm,psci-suspend-param = <0x10000>;
+ };
+
+ big_cpu_sleep: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "c2";
+ entry-latency-us = <235>;
+ exit-latency-us = <220>;
+ min-residency-us = <3500>;
+ arm,psci-suspend-param = <0x10000>;
+ };
+
+ prime_cpu_sleep: cpu-sleep-2 {
+ compatible = "arm,idle-state";
+ idle-state-name = "c2";
+ entry-latency-us = <150>;
+ exit-latency-us = <190>;
+ min-residency-us = <2500>;
+ arm,psci-suspend-param = <0x10000>;
+ };
+ };
+ };
+
+ pmu-a510 {
+ compatible = "arm,cortex-a510-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-a710 {
+ compatible = "arm,cortex-a710-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
+ pmu-x2 {
+ compatible = "arm,cortex-x2-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chipid@10000000 {
+ compatible = "samsung,exynos2200-chipid",
+ "samsung,exynos850-chipid";
+ reg = <0x0 0x10000000 0x0 0x24>;
+ };
+
+ cmu_peris: clock-controller@10020000 {
+ compatible = "samsung,exynos2200-cmu-peris";
+ reg = <0x0 0x10020000 0x0 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>,
+ <&cmu_top CLK_DOUT_CMU_PERIS_NOC>,
+ <&cmu_top CLK_DOUT_CMU_PERIS_GIC>;
+ clock-names = "tcxo_div3",
+ "noc",
+ "gic";
+ };
+
+ mct_peris: timer@10040000 {
+ compatible = "samsung,exynos2200-mct-peris",
+ "samsung,exynos4210-mct";
+ reg = <0x0 0x10040000 0x0 0x800>;
+ clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GIC>;
+ clock-names = "fin_pll", "mct";
+ interrupts = <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 947 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 948 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@10200000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x10200000 0x0 0x10000>, /* GICD */
+ <0x0 0x10240000 0x0 0x200000>; /* GICR * 8 */
+
+ #interrupt-cells = <4>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6>;
+ };
+
+ ppi_cluster2: interrupt-partition-2 {
+ affinity = <&cpu7>;
+ };
+ };
+ };
+
+ cmu_peric0: clock-controller@10400000 {
+ compatible = "samsung,exynos2200-cmu-peric0";
+ reg = <0x0 0x10400000 0x0 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_NOC>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_IP0>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_IP1>;
+ clock-names = "oscclk", "noc", "ip0", "ip1";
+ };
+
+ syscon_peric0: syscon@10420000 {
+ compatible = "samsung,exynos2200-peric0-sysreg", "syscon";
+ reg = <0x0 0x10420000 0x0 0x2000>;
+ };
+
+ pinctrl_peric0: pinctrl@10430000 {
+ compatible = "samsung,exynos2200-pinctrl";
+ reg = <0x0 0x10430000 0x0 0x1000>;
+ };
+
+ cmu_peric1: clock-controller@10700000 {
+ compatible = "samsung,exynos2200-cmu-peric1";
+ reg = <0x0 0x10700000 0x0 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_NOC>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_IP0>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_IP1>;
+ clock-names = "oscclk", "noc", "ip0", "ip1";
+ };
+
+ syscon_peric1: syscon@10720000 {
+ compatible = "samsung,exynos2200-peric1-sysreg", "syscon";
+ reg = <0x0 0x10720000 0x0 0x2000>;
+ };
+
+ pinctrl_peric1: pinctrl@10730000 {
+ compatible = "samsung,exynos2200-pinctrl";
+ reg = <0x0 0x10730000 0x0 0x1000>;
+ };
+
+ cmu_hsi0: clock-controller@10a00000 {
+ compatible = "samsung,exynos2200-cmu-hsi0";
+ reg = <0x0 0x10a00000 0x0 0x8000>;
+ #clock-cells = <1>;
+ };
+
+ usb32drd: phy@10aa0000 {
+ compatible = "samsung,exynos2200-usb32drd-phy";
+ reg = <0x0 0x10aa0000 0x0 0x10000>;
+
+ clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>;
+ clock-names = "phy";
+
+ #phy-cells = <1>;
+ phys = <&usb_hsphy>;
+ phy-names = "hs";
+
+ samsung,pmu-syscon = <&pmu_system_controller>;
+
+ status = "disabled";
+ };
+
+ usb_hsphy: phy@10ab0000 {
+ compatible = "samsung,exynos2200-eusb2-phy";
+ reg = <0x0 0x10ab0000 0x0 0x10000>;
+
+ clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>,
+ <&cmu_hsi0 CLK_MOUT_HSI0_NOC>,
+ <&cmu_hsi0 CLK_DOUT_DIV_CLK_HSI0_EUSB>;
+ clock-names = "ref", "bus", "ctrl";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb: usb@10b00000 {
+ compatible = "samsung,exynos2200-dwusb3";
+ ranges = <0x0 0x0 0x10b00000 0x10000>;
+
+ clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>;
+ clock-names = "link_aclk";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+
+ usb_dwc3: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+
+ clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>;
+ clock-names = "ref";
+
+ interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ phys = <&usb32drd 0>;
+ phy-names = "usb2-phy";
+
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,gfladj-refclk-lpm-sel-quirk;
+ snps,has-lpm-erratum;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,usb3_lpm_capable;
+ };
+ };
+
+ cmu_ufs: clock-controller@11000000 {
+ compatible = "samsung,exynos2200-cmu-ufs";
+ reg = <0x0 0x11000000 0x0 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top CLK_DOUT_CMU_UFS_NOC>,
+ <&cmu_top CLK_MOUT_CMU_UFS_MMC_CARD>,
+ <&cmu_top CLK_DOUT_CMU_UFS_UFS_EMBD>;
+ clock-names = "oscclk", "noc", "mmc", "ufs";
+ };
+
+ syscon_ufs: syscon@11020000 {
+ compatible = "samsung,exynos2200-ufs-sysreg", "syscon";
+ reg = <0x0 0x11020000 0x0 0x2000>;
+ };
+
+ pinctrl_ufs: pinctrl@11040000 {
+ compatible = "samsung,exynos2200-pinctrl";
+ reg = <0x0 0x11040000 0x0 0x1000>;
+ };
+
+ pinctrl_hsi1ufs: pinctrl@11060000 {
+ compatible = "samsung,exynos2200-pinctrl";
+ reg = <0x0 0x11060000 0x0 0x1000>;
+ };
+
+ pinctrl_hsi1: pinctrl@11240000 {
+ compatible = "samsung,exynos2200-pinctrl";
+ reg = <0x0 0x11240000 0x0 0x1000>;
+ };
+
+ cmu_peric2: clock-controller@11c00000 {
+ compatible = "samsung,exynos2200-cmu-peric2";
+ reg = <0x0 0x11c00000 0x0 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top CLK_DOUT_CMU_PERIC2_NOC>,
+ <&cmu_top CLK_DOUT_CMU_PERIC2_IP0>,
+ <&cmu_top CLK_DOUT_CMU_PERIC2_IP1>;
+ clock-names = "oscclk", "noc", "ip0", "ip1";
+ };
+
+ syscon_peric2: syscon@11c20000 {
+ compatible = "samsung,exynos2200-peric2-sysreg", "syscon";
+ reg = <0x0 0x11c20000 0x0 0x4000>;
+ };
+
+ pinctrl_peric2: pinctrl@11c30000 {
+ compatible = "samsung,exynos2200-pinctrl";
+ reg = <0x0 0x11c30000 0x0 0x1000>;
+ };
+
+ cmu_cmgp: clock-controller@14e00000 {
+ compatible = "samsung,exynos2200-cmu-cmgp";
+ reg = <0x0 0x14e00000 0x0 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_alive CLK_DOUT_ALIVE_CMGP_NOC>,
+ <&cmu_alive CLK_DOUT_ALIVE_CMGP_PERI>;
+ clock-names = "oscclk", "noc", "peri";
+ };
+
+ syscon_cmgp: syscon@14e20000 {
+ compatible = "samsung,exynos2200-cmgp-sysreg", "syscon";
+ reg = <0x0 0x14e20000 0x0 0x2000>;
+ };
+
+ pinctrl_cmgp: pinctrl@14e30000 {
+ compatible = "samsung,exynos2200-pinctrl";
+ reg = <0x0 0x14e30000 0x0 0x1000>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos2200-wakeup-eint",
+ "samsung,exynos850-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
+ };
+ };
+
+ cmu_vts: clock-controller@15300000 {
+ compatible = "samsung,exynos2200-cmu-vts";
+ reg = <0x0 0x15300000 0x0 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top CLK_DOUT_CMU_VTS_DMIC>;
+ clock-names = "oscclk", "dmic";
+ };
+
+ pinctrl_vts: pinctrl@15320000 {
+ compatible = "samsung,exynos2200-pinctrl";
+ reg = <0x0 0x15320000 0x0 0x1000>;
+ };
+
+ cmu_alive: clock-controller@15800000 {
+ compatible = "samsung,exynos2200-cmu-alive";
+ reg = <0x0 0x15800000 0x0 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top CLK_DOUT_CMU_ALIVE_NOC>;
+ clock-names = "oscclk", "noc";
+ };
+
+ pinctrl_alive: pinctrl@15850000 {
+ compatible = "samsung,exynos2200-pinctrl";
+ reg = <0x0 0x15850000 0x0 0x1000>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos2200-wakeup-eint",
+ "samsung,exynos850-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
+ };
+ };
+
+ pmu_system_controller: system-controller@15860000 {
+ compatible = "samsung,exynos2200-pmu",
+ "samsung,exynos7-pmu", "syscon";
+ reg = <0x0 0x15860000 0x0 0x10000>;
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ offset = <0x3c00>; /* SYSTEM_CONFIGURATION */
+ mask = <0x2>; /* SWRESET_SYSTEM */
+ value = <0x2>; /* reset value */
+ };
+ };
+
+ cmu_top: clock-controller@1a320000 {
+ compatible = "samsung,exynos2200-cmu-top";
+ reg = <0x0 0x1a320000 0x0 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>;
+ clock-names = "oscclk";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ /*
+ * Non-updatable, broken stock Samsung bootloader does not
+ * configure CNTFRQ_EL0
+ */
+ clock-frequency = <25600000>;
+ };
+};
+
+#include "exynos2200-pinctrl.dtsi"
generated by cgit (git 2.34.1) at 2025-07-30 21:26:45 +0000