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-rw-r--r--arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi112
-rw-r--r--arch/arm64/boot/dts/st/stm32mp251.dtsi758
-rw-r--r--arch/arm64/boot/dts/st/stm32mp257f-ev1.dts98
3 files changed, 966 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 8fdd5f020425..5ac9e72478dd 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -82,6 +82,104 @@
};
};
+ ospi_port1_clk_pins_a: ospi-port1-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, AF10)>; /* OSPI1_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ ospi_port1_clk_sleep_pins_a: ospi-port1-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, ANALOG)>; /* OSPI1_CLK */
+ };
+ };
+
+ ospi_port1_cs0_pins_a: ospi-port1-cs0-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 3, AF10)>; /* OSPI_NCS0 */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ ospi_port1_cs0_sleep_pins_a: ospi-port1-cs0-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 3, ANALOG)>; /* OSPI_NCS0 */
+ };
+ };
+
+ ospi_port1_io03_pins_a: ospi-port1-io03-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, AF10)>, /* OSPI_IO0 */
+ <STM32_PINMUX('D', 5, AF10)>, /* OSPI_IO1 */
+ <STM32_PINMUX('D', 6, AF10)>, /* OSPI_IO2 */
+ <STM32_PINMUX('D', 7, AF10)>; /* OSPI_IO3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ ospi_port1_io03_sleep_pins_a: ospi-port1-io03-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* OSPI_IO0 */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* OSPI_IO1 */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* OSPI_IO2 */
+ <STM32_PINMUX('D', 7, ANALOG)>; /* OSPI_IO3 */
+ };
+ };
+
+ pwm3_pins_a: pwm3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 15, AF7)>; /* TIM3_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm3_sleep_pins_a: pwm3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 15, ANALOG)>; /* TIM3_CH2 */
+ };
+ };
+
+ pwm8_pins_a: pwm8-0 {
+ pins {
+ pinmux = <STM32_PINMUX('J', 5, AF8)>, /* TIM8_CH1 */
+ <STM32_PINMUX('J', 4, AF8)>; /* TIM8_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm8_sleep_pins_a: pwm8-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('J', 5, ANALOG)>, /* TIM8_CH1 */
+ <STM32_PINMUX('J', 4, ANALOG)>; /* TIM8_CH4 */
+ };
+ };
+
+ pwm12_pins_a: pwm12-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 11, AF9)>; /* TIM12_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm12_sleep_pins_a: pwm12-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 11, ANALOG)>; /* TIM12_CH2 */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
@@ -158,6 +256,20 @@
};
};
+ tim10_counter_pins_a: tim10-counter-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, AF9)>; /* TIM10_CH1 */
+ bias-disable;
+ };
+ };
+
+ tim10_counter_sleep_pins_a: tim10-counter-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* TIM10_CH1 */
+ bias-disable;
+ };
+ };
+
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 87110f91e489..303abf915b8e 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -150,7 +150,7 @@
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- always-on;
+ arm,no-tick-in-suspend;
};
soc@0 {
@@ -229,6 +229,60 @@
#dma-cells = <3>;
};
+ ommanager: ommanager@40500000 {
+ compatible = "st,stm32mp25-omm";
+ reg = <0x40500000 0x400>, <0x60000000 0x10000000>;
+ reg-names = "regs", "memory_map";
+ ranges = <0 0 0x40430000 0x400>,
+ <1 0 0x40440000 0x400>;
+ clocks = <&rcc CK_BUS_OSPIIOM>,
+ <&scmi_clk CK_SCMI_OSPI1>,
+ <&scmi_clk CK_SCMI_OSPI2>;
+ clock-names = "omm", "ospi1", "ospi2";
+ resets = <&rcc OSPIIOM_R>,
+ <&scmi_reset RST_SCMI_OSPI1>,
+ <&scmi_reset RST_SCMI_OSPI2>;
+ reset-names = "omm", "ospi1", "ospi2";
+ access-controllers = <&rifsc 111>;
+ power-domains = <&CLUSTER_PD>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ st,syscfg-amcr = <&syscfg 0x2c00 0x7>;
+ status = "disabled";
+
+ ospi1: spi@0 {
+ compatible = "st,stm32mp25-ospi";
+ reg = <0 0 0x400>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&hpdma 2 0x62 0x3121>,
+ <&hpdma 2 0x42 0x3112>;
+ dma-names = "tx", "rx";
+ clocks = <&scmi_clk CK_SCMI_OSPI1>;
+ resets = <&scmi_reset RST_SCMI_OSPI1>,
+ <&scmi_reset RST_SCMI_OSPI1DLL>;
+ access-controllers = <&rifsc 74>;
+ power-domains = <&CLUSTER_PD>;
+ st,syscfg-dlyb = <&syscfg 0x1000>;
+ status = "disabled";
+ };
+
+ ospi2: spi@1 {
+ compatible = "st,stm32mp25-ospi";
+ reg = <1 0 0x400>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&hpdma 3 0x62 0x3121>,
+ <&hpdma 3 0x42 0x3112>;
+ dma-names = "tx", "rx";
+ clocks = <&scmi_clk CK_SCMI_OSPI2>;
+ resets = <&scmi_reset RST_SCMI_OSPI2>,
+ <&scmi_reset RST_SCMI_OSPI2DLL>;
+ access-controllers = <&rifsc 75>;
+ power-domains = <&CLUSTER_PD>;
+ st,syscfg-dlyb = <&syscfg 0x1400>;
+ status = "disabled";
+ };
+ };
+
rifsc: bus@42080000 {
compatible = "st,stm32mp25-rifsc", "simple-bus";
reg = <0x42080000 0x1000>;
@@ -237,6 +291,345 @@
#access-controller-cells = <1>;
ranges;
+ timers2: timer@40000000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40000000 0x400>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM2>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 1>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@1 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+
+ timers3: timer@40010000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40010000 0x400>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM3>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 2>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@2 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
+ timers4: timer@40020000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40020000 0x400>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM4>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 3>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@3 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <3>;
+ status = "disabled";
+ };
+ };
+
+ timers5: timer@40030000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40030000 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM5>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 4>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@4 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+
+ timers6: timer@40040000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40040000 0x400>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM6>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 5>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ timer@5 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ timers7: timer@40050000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40050000 0x400>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM7>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 6>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ timer@6 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <6>;
+ status = "disabled";
+ };
+ };
+
+ timers12: timer@40060000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40060000 0x400>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM12>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 10>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@11 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <11>;
+ status = "disabled";
+ };
+ };
+
+ timers13: timer@40070000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40070000 0x400>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM13>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 11>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@12 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <12>;
+ status = "disabled";
+ };
+ };
+
+ timers14: timer@40080000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40080000 0x400>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM14>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 12>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@13 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <13>;
+ status = "disabled";
+ };
+ };
+
+ lptimer1: timer@40090000 {
+ compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
+ reg = <0x40090000 0x400>;
+ interrupts-extended = <&exti1 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_LPTIM1>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 17>;
+ power-domains = <&RET_PD>;
+ wakeup-source;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+
+ trigger@0 {
+ compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+ };
+
+ lptimer2: timer@400a0000 {
+ compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
+ reg = <0x400a0000 0x400>;
+ interrupts-extended = <&exti1 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_LPTIM2>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 18>;
+ power-domains = <&RET_PD>;
+ wakeup-source;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+
+ trigger@1 {
+ compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+
i2s2: audio-controller@400b0000 {
compatible = "st,stm32mp25-i2s";
reg = <0x400b0000 0x400>;
@@ -471,6 +864,136 @@
status = "disabled";
};
+ timers10: timer@401c0000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x401c0000 0x400>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM10>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 8>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@9 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <9>;
+ status = "disabled";
+ };
+ };
+
+ timers11: timer@401d0000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x401d0000 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM11>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 9>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@10 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <10>;
+ status = "disabled";
+ };
+ };
+
+ timers1: timer@40200000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40200000 0x400>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "brk", "up", "trg-com", "cc";
+ clocks = <&rcc CK_KER_TIM1>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 0>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@0 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+ };
+
+ timers8: timer@40210000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40210000 0x400>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "brk", "up", "trg-com", "cc";
+ clocks = <&rcc CK_KER_TIM8>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 7>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@7 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <7>;
+ status = "disabled";
+ };
+ };
+
usart6: serial@40220000 {
compatible = "st,stm32h7-uart";
reg = <0x40220000 0x400>;
@@ -528,6 +1051,99 @@
status = "disabled";
};
+ timers15: timer@40250000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40250000 0x400>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM15>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 13>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@14 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <14>;
+ status = "disabled";
+ };
+ };
+
+ timers16: timer@40260000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40260000 0x400>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM16>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 14>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@15 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <15>;
+ status = "disabled";
+ };
+ };
+
+ timers17: timer@40270000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40270000 0x400>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc CK_KER_TIM17>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 15>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@16 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <16>;
+ status = "disabled";
+ };
+ };
+
spi5: spi@40280000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -657,6 +1273,40 @@
status = "disabled";
};
+ timers20: timer@40320000 {
+ compatible = "st,stm32mp25-timers";
+ reg = <0x40320000 0x400>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "brk", "up", "trg-com", "cc";
+ clocks = <&rcc CK_KER_TIM20>;
+ clock-names = "int";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 16>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-timer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@19 {
+ compatible = "st,stm32mp25-timer-trigger";
+ reg = <19>;
+ status = "disabled";
+ };
+ };
+
usart1: serial@40330000 {
compatible = "st,stm32h7-uart";
reg = <0x40330000 0x400>;
@@ -798,6 +1448,111 @@
status = "disabled";
};
+ lptimer3: timer@46050000 {
+ compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
+ reg = <0x46050000 0x400>;
+ interrupts-extended = <&exti2 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_LPTIM3>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 19>;
+ wakeup-source;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+
+ trigger@2 {
+ compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
+ lptimer4: timer@46060000 {
+ compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
+ reg = <0x46060000 0x400>;
+ interrupts-extended = <&exti2 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_LPTIM4>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 20>;
+ wakeup-source;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+
+ trigger@3 {
+ compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger";
+ reg = <3>;
+ status = "disabled";
+ };
+ };
+
+ lptimer5: timer@46070000 {
+ compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
+ reg = <0x46070000 0x400>;
+ interrupts-extended = <&exti2 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_LPTIM5>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 21>;
+ wakeup-source;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+
+ trigger@4 {
+ compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger";
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+
csi: csi@48020000 {
compatible = "st,stm32mp25-csi";
reg = <0x48020000 0x2000>;
@@ -1264,7 +2019,6 @@
st,bank-ioport = <11>;
status = "disabled";
};
-
};
exti2: interrupt-controller@46230000 {
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index 1b88485a62a1..836b1958ce65 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -80,6 +80,11 @@
reg = <0x0 0x80000000 0x0 0x4000000>;
no-map;
};
+
+ mm_ospi1: mm-ospi@60000000 {
+ reg = <0x0 0x60000000 0x0 0x10000000>;
+ no-map;
+ };
};
};
@@ -190,6 +195,41 @@
status = "disabled";
};
+&ommanager {
+ memory-region = <&mm_ospi1>;
+ pinctrl-0 = <&ospi_port1_clk_pins_a
+ &ospi_port1_io03_pins_a
+ &ospi_port1_cs0_pins_a>;
+ pinctrl-1 = <&ospi_port1_clk_sleep_pins_a
+ &ospi_port1_io03_sleep_pins_a
+ &ospi_port1_cs0_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+
+ spi@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ memory-region = <&mm_ospi1>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ spi-max-frequency = <50000000>;
+ };
+ };
+};
+
+/* use LPTIMER with tick broadcast for suspend mode */
+&lptimer3 {
+ status = "okay";
+ timer {
+ status = "okay";
+ };
+};
+
&rtc {
status = "okay";
};
@@ -253,6 +293,64 @@
status = "disabled";
};
+&timers3 {
+ status = "disabled";
+ counter {
+ status = "okay";
+ };
+ pwm {
+ pinctrl-0 = <&pwm3_pins_a>;
+ pinctrl-1 = <&pwm3_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@2 {
+ status = "okay";
+ };
+};
+
+&timers8 {
+ status = "disabled";
+ counter {
+ status = "okay";
+ };
+ pwm {
+ pinctrl-0 = <&pwm8_pins_a>;
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@7 {
+ status = "okay";
+ };
+};
+
+&timers10 {
+ status = "disabled";
+ counter {
+ pinctrl-0 = <&tim10_counter_pins_a>;
+ pinctrl-1 = <&tim10_counter_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+};
+
+&timers12 {
+ status = "disabled";
+ counter {
+ status = "okay";
+ };
+ pwm {
+ pinctrl-0 = <&pwm12_pins_a>;
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@11 {
+ status = "okay";
+ };
+};
+
&usart2 {
pinctrl-names = "default", "idle", "sleep";
pinctrl-0 = <&usart2_pins_a>;
generated by cgit (git 2.34.1) at 2025-07-30 19:14:13 +0000