diff options
Diffstat (limited to 'arch/mips/include/asm/mach-loongson32')
| -rw-r--r-- | arch/mips/include/asm/mach-loongson32/irq.h | 107 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-loongson32/loongson1.h | 50 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-loongson32/platform.h | 23 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-loongson32/regs-mux.h | 124 |
4 files changed, 0 insertions, 304 deletions
diff --git a/arch/mips/include/asm/mach-loongson32/irq.h b/arch/mips/include/asm/mach-loongson32/irq.h deleted file mode 100644 index 6115f025ba21..000000000000 --- a/arch/mips/include/asm/mach-loongson32/irq.h +++ /dev/null @@ -1,107 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> - * - * IRQ mappings for Loongson 1 - */ - -#ifndef __ASM_MACH_LOONGSON32_IRQ_H -#define __ASM_MACH_LOONGSON32_IRQ_H - -/* - * CPU core Interrupt Numbers - */ -#define MIPS_CPU_IRQ_BASE 0 -#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) - -#define SOFTINT0_IRQ MIPS_CPU_IRQ(0) -#define SOFTINT1_IRQ MIPS_CPU_IRQ(1) -#define INT0_IRQ MIPS_CPU_IRQ(2) -#define INT1_IRQ MIPS_CPU_IRQ(3) -#define INT2_IRQ MIPS_CPU_IRQ(4) -#define INT3_IRQ MIPS_CPU_IRQ(5) -#define INT4_IRQ MIPS_CPU_IRQ(6) -#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */ - -#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE) - -/* - * INT0~3 Interrupt Numbers - */ -#define LS1X_IRQ_BASE MIPS_CPU_IRQS -#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) - -#define LS1X_UART0_IRQ LS1X_IRQ(0, 2) -#if defined(CONFIG_LOONGSON1_LS1B) -#define LS1X_UART1_IRQ LS1X_IRQ(0, 3) -#define LS1X_UART2_IRQ LS1X_IRQ(0, 4) -#define LS1X_UART3_IRQ LS1X_IRQ(0, 5) -#elif defined(CONFIG_LOONGSON1_LS1C) -#define LS1X_UART1_IRQ LS1X_IRQ(0, 4) -#define LS1X_UART2_IRQ LS1X_IRQ(0, 5) -#endif -#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) -#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) -#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) -#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9) -#define LS1X_AC97_IRQ LS1X_IRQ(0, 10) -#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) -#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) -#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) -#if defined(CONFIG_LOONGSON1_LS1C) -#define LS1X_NAND_IRQ LS1X_IRQ(0, 16) -#endif -#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) -#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) -#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) -#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20) -#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) -#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) -#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) -#if defined(CONFIG_LOONGSON1_LS1B) -#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) -#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) -#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) -#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) -#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) -#define LS1X_UART4_IRQ LS1X_IRQ(0, 29) -#define LS1X_UART5_IRQ LS1X_IRQ(0, 30) -#elif defined(CONFIG_LOONGSON1_LS1C) -#define LS1X_UART3_IRQ LS1X_IRQ(0, 29) -#define LS1X_ADC_IRQ LS1X_IRQ(0, 30) -#define LS1X_SDIO_IRQ LS1X_IRQ(0, 31) -#endif - -#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) -#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) -#if defined(CONFIG_LOONGSON1_LS1B) -#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) -#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) -#elif defined(CONFIG_LOONGSON1_LS1C) -#define LS1X_OTG_IRQ LS1X_IRQ(1, 2) -#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3) -#define LS1X_CAM_IRQ LS1X_IRQ(1, 4) -#define LS1X_UART4_IRQ LS1X_IRQ(1, 5) -#define LS1X_UART5_IRQ LS1X_IRQ(1, 6) -#define LS1X_UART6_IRQ LS1X_IRQ(1, 7) -#define LS1X_UART7_IRQ LS1X_IRQ(1, 8) -#define LS1X_UART8_IRQ LS1X_IRQ(1, 9) -#define LS1X_UART9_IRQ LS1X_IRQ(1, 13) -#define LS1X_UART10_IRQ LS1X_IRQ(1, 14) -#define LS1X_UART11_IRQ LS1X_IRQ(1, 15) -#define LS1X_I2C0_IRQ LS1X_IRQ(1, 17) -#define LS1X_I2C1_IRQ LS1X_IRQ(1, 18) -#define LS1X_I2C2_IRQ LS1X_IRQ(1, 19) -#endif - -#if defined(CONFIG_LOONGSON1_LS1B) -#define INTN 4 -#elif defined(CONFIG_LOONGSON1_LS1C) -#define INTN 5 -#endif - -#define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE) - -#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) - -#endif /* __ASM_MACH_LOONGSON32_IRQ_H */ diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h deleted file mode 100644 index 84f45461c832..000000000000 --- a/arch/mips/include/asm/mach-loongson32/loongson1.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> - * - * Register mappings for Loongson 1 - */ - -#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H -#define __ASM_MACH_LOONGSON32_LOONGSON1_H - -#if defined(CONFIG_LOONGSON1_LS1B) -#define DEFAULT_MEMSIZE 64 /* If no memsize provided */ -#elif defined(CONFIG_LOONGSON1_LS1C) -#define DEFAULT_MEMSIZE 32 -#endif - -/* Loongson 1 Register Bases */ -#define LS1X_MUX_BASE 0x1fd00420 -#define LS1X_INTC_BASE 0x1fd01040 -#define LS1X_GPIO0_BASE 0x1fd010c0 -#define LS1X_GPIO1_BASE 0x1fd010c4 -#define LS1X_DMAC_BASE 0x1fd01160 -#define LS1X_CBUS_BASE 0x1fd011c0 -#define LS1X_EHCI_BASE 0x1fe00000 -#define LS1X_OHCI_BASE 0x1fe08000 -#define LS1X_GMAC0_BASE 0x1fe10000 -#define LS1X_GMAC1_BASE 0x1fe20000 - -#define LS1X_UART0_BASE 0x1fe40000 -#define LS1X_UART1_BASE 0x1fe44000 -#define LS1X_UART2_BASE 0x1fe48000 -#define LS1X_UART3_BASE 0x1fe4c000 -#define LS1X_CAN0_BASE 0x1fe50000 -#define LS1X_CAN1_BASE 0x1fe54000 -#define LS1X_I2C0_BASE 0x1fe58000 -#define LS1X_I2C1_BASE 0x1fe68000 -#define LS1X_I2C2_BASE 0x1fe70000 -#define LS1X_PWM0_BASE 0x1fe5c000 -#define LS1X_PWM1_BASE 0x1fe5c010 -#define LS1X_PWM2_BASE 0x1fe5c020 -#define LS1X_PWM3_BASE 0x1fe5c030 -#define LS1X_WDT_BASE 0x1fe5c060 -#define LS1X_RTC_BASE 0x1fe64000 -#define LS1X_AC97_BASE 0x1fe74000 -#define LS1X_NAND_BASE 0x1fe78000 -#define LS1X_CLK_BASE 0x1fe78030 - -#include <regs-mux.h> - -#endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */ diff --git a/arch/mips/include/asm/mach-loongson32/platform.h b/arch/mips/include/asm/mach-loongson32/platform.h deleted file mode 100644 index f74292b13bc3..000000000000 --- a/arch/mips/include/asm/mach-loongson32/platform.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> - */ - -#ifndef __ASM_MACH_LOONGSON32_PLATFORM_H -#define __ASM_MACH_LOONGSON32_PLATFORM_H - -#include <linux/platform_device.h> - -extern struct platform_device ls1x_uart_pdev; -extern struct platform_device ls1x_eth0_pdev; -extern struct platform_device ls1x_eth1_pdev; -extern struct platform_device ls1x_ehci_pdev; -extern struct platform_device ls1x_gpio0_pdev; -extern struct platform_device ls1x_gpio1_pdev; -extern struct platform_device ls1x_rtc_pdev; -extern struct platform_device ls1x_wdt_pdev; - -void __init ls1x_rtc_set_extclk(struct platform_device *pdev); -void __init ls1x_serial_set_uartclk(struct platform_device *pdev); - -#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */ diff --git a/arch/mips/include/asm/mach-loongson32/regs-mux.h b/arch/mips/include/asm/mach-loongson32/regs-mux.h deleted file mode 100644 index 95788a4f03a0..000000000000 --- a/arch/mips/include/asm/mach-loongson32/regs-mux.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com> - * - * Loongson 1 MUX Register Definitions. - */ - -#ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H -#define __ASM_MACH_LOONGSON32_REGS_MUX_H - -#define LS1X_MUX_REG(x) \ - ((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x))) - -#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0) -#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4) - -#if defined(CONFIG_LOONGSON1_LS1B) -/* MUX CTRL0 Register Bits */ -#define UART0_USE_PWM23 BIT(28) -#define UART0_USE_PWM01 BIT(27) -#define UART1_USE_LCD0_5_6_11 BIT(26) -#define I2C2_USE_CAN1 BIT(25) -#define I2C1_USE_CAN0 BIT(24) -#define NAND3_USE_UART5 BIT(23) -#define NAND3_USE_UART4 BIT(22) -#define NAND3_USE_UART1_DAT BIT(21) -#define NAND3_USE_UART1_CTS BIT(20) -#define NAND3_USE_PWM23 BIT(19) -#define NAND3_USE_PWM01 BIT(18) -#define NAND2_USE_UART5 BIT(17) -#define NAND2_USE_UART4 BIT(16) -#define NAND2_USE_UART1_DAT BIT(15) -#define NAND2_USE_UART1_CTS BIT(14) -#define NAND2_USE_PWM23 BIT(13) -#define NAND2_USE_PWM01 BIT(12) -#define NAND1_USE_UART5 BIT(11) -#define NAND1_USE_UART4 BIT(10) -#define NAND1_USE_UART1_DAT BIT(9) -#define NAND1_USE_UART1_CTS BIT(8) -#define NAND1_USE_PWM23 BIT(7) -#define NAND1_USE_PWM01 BIT(6) -#define GMAC1_USE_UART1 BIT(4) -#define GMAC1_USE_UART0 BIT(3) -#define LCD_USE_UART0_DAT BIT(2) -#define LCD_USE_UART15 BIT(1) -#define LCD_USE_UART0 BIT(0) - -/* MUX CTRL1 Register Bits */ -#define USB_RESET BIT(31) -#define SPI1_CS_USE_PWM01 BIT(24) -#define SPI1_USE_CAN BIT(23) -#define DISABLE_DDR_CONFSPACE BIT(20) -#define DDR32TO16EN BIT(16) -#define GMAC1_SHUT BIT(13) -#define GMAC0_SHUT BIT(12) -#define USB_SHUT BIT(11) -#define UART1_3_USE_CAN1 BIT(5) -#define UART1_2_USE_CAN0 BIT(4) -#define GMAC1_USE_TXCLK BIT(3) -#define GMAC0_USE_TXCLK BIT(2) -#define GMAC1_USE_PWM23 BIT(1) -#define GMAC0_USE_PWM01 BIT(0) - -#elif defined(CONFIG_LOONGSON1_LS1C) - -/* SHUT_CTRL Register Bits */ -#define UART_SPLIT GENMASK(31, 30) -#define OUTPUT_CLK GENMASK(29, 26) -#define ADC_SHUT BIT(25) -#define SDIO_SHUT BIT(24) -#define DMA2_SHUT BIT(23) -#define DMA1_SHUT BIT(22) -#define DMA0_SHUT BIT(21) -#define SPI1_SHUT BIT(20) -#define SPI0_SHUT BIT(19) -#define I2C2_SHUT BIT(18) -#define I2C1_SHUT BIT(17) -#define I2C0_SHUT BIT(16) -#define AC97_SHUT BIT(15) -#define I2S_SHUT BIT(14) -#define UART3_SHUT BIT(13) -#define UART2_SHUT BIT(12) -#define UART1_SHUT BIT(11) -#define UART0_SHUT BIT(10) -#define CAN1_SHUT BIT(9) -#define CAN0_SHUT BIT(8) -#define ECC_SHUT BIT(7) -#define GMAC_SHUT BIT(6) -#define USBHOST_SHUT BIT(5) -#define USBOTG_SHUT BIT(4) -#define SDRAM_SHUT BIT(3) -#define SRAM_SHUT BIT(2) -#define CAM_SHUT BIT(1) -#define LCD_SHUT BIT(0) - -#define UART_SPLIT_SHIFT 30 -#define OUTPUT_CLK_SHIFT 26 - -/* MISC_CTRL Register Bits */ -#define USBHOST_RSTN BIT(31) -#define PHY_INTF_SELI GENMASK(30, 28) -#define AC97_EN BIT(25) -#define SDIO_DMA_EN GENMASK(24, 23) -#define ADC_DMA_EN BIT(22) -#define SDIO_USE_SPI1 BIT(17) -#define SDIO_USE_SPI0 BIT(16) -#define SRAM_CTRL GENMASK(15, 0) - -#define PHY_INTF_SELI_SHIFT 28 -#define SDIO_DMA_EN_SHIFT 23 -#define SRAM_CTRL_SHIFT 0 - -#define LS1X_CBUS_REG(n, x) \ - ((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x))) - -#define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00) -#define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10) -#define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20) -#define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30) -#define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40) - -#endif - -#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */ |