diff options
Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.h | 66 |
1 files changed, 10 insertions, 56 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index b6eece5ffa20..0a71c5ec24b6 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -82,6 +82,8 @@ #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) +#define MSTOP(name, bitmask) ((CPG_##name##_MSTOP) << 16 | (bitmask)) + #define EXTAL_FREQ_IN_MEGA_HZ (24) /** @@ -201,6 +203,7 @@ enum clk_types { * @name: handle between common and hardware-specific interfaces * @id: clock index in array containing all Core and Module Clocks * @parent: id of parent clock + * @mstop_conf: MSTOP configuration * @off: register offset * @bit: ON/MON bit * @is_coupled: flag to indicate coupled clock @@ -209,26 +212,28 @@ struct rzg2l_mod_clk { const char *name; unsigned int id; unsigned int parent; + u32 mstop_conf; u16 off; u8 bit; bool is_coupled; }; -#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ +#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \ { \ .name = _name, \ .id = MOD_CLK_BASE + (_id), \ .parent = (_parent), \ + .mstop_conf = (_mstop_conf), \ .off = (_off), \ .bit = (_bit), \ .is_coupled = (_is_coupled), \ } -#define DEF_MOD(_name, _id, _parent, _off, _bit) \ - DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false) +#define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \ + DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, false) -#define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ - DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true) +#define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \ + DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, true) /** * struct rzg2l_reset - Reset definitions @@ -253,51 +258,6 @@ struct rzg2l_reset { DEF_RST_MON(_id, _off, _bit, -1) /** - * struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure - * @off: register offset - * @mask: register mask - */ -struct rzg2l_cpg_reg_conf { - u16 off; - u16 mask; -}; - -#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) }) - -/** - * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure - * @mstop: MSTOP register configuration - */ -struct rzg2l_cpg_pm_domain_conf { - struct rzg2l_cpg_reg_conf mstop; -}; - -/** - * struct rzg2l_cpg_pm_domain_init_data - PM domain init data - * @name: PM domain name - * @conf: PM domain configuration - * @genpd_flags: genpd flags (see GENPD_FLAG_*) - * @id: PM domain ID (similar to the ones defined in - * include/dt-bindings/clock/<soc-id>-cpg.h) - */ -struct rzg2l_cpg_pm_domain_init_data { - const char * const name; - struct rzg2l_cpg_pm_domain_conf conf; - u32 genpd_flags; - u16 id; -}; - -#define DEF_PD(_name, _id, _mstop_conf, _flags) \ - { \ - .name = (_name), \ - .id = (_id), \ - .conf = { \ - .mstop = (_mstop_conf), \ - }, \ - .genpd_flags = (_flags), \ - } - -/** * struct rzg2l_cpg_info - SoC-specific CPG Description * * @core_clks: Array of Core Clock definitions @@ -315,8 +275,6 @@ struct rzg2l_cpg_pm_domain_init_data { * @crit_mod_clks: Array with Module Clock IDs of critical clocks that * should not be disabled without a knowledgeable driver * @num_crit_mod_clks: Number of entries in crit_mod_clks[] - * @pm_domains: PM domains init data array - * @num_pm_domains: Number of PM domains * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers */ struct rzg2l_cpg_info { @@ -343,10 +301,6 @@ struct rzg2l_cpg_info { const unsigned int *crit_mod_clks; unsigned int num_crit_mod_clks; - /* Power domain. */ - const struct rzg2l_cpg_pm_domain_init_data *pm_domains; - unsigned int num_pm_domains; - bool has_clk_mon_regs; }; |