diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/include/nvif')
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/chan.h | 76 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/cl0080.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/class.h | 35 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/object.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/push.h | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/push906f.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/pushc97b.h | 18 |
7 files changed, 145 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/chan.h b/drivers/gpu/drm/nouveau/include/nvif/chan.h new file mode 100644 index 000000000000..c329a29068d5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/chan.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. + */ +#ifndef __NVIF_CHAN_H__ +#define __NVIF_CHAN_H__ +#include "push.h" + +struct nvif_chan { + const struct nvif_chan_func { + struct { + u32 (*read_get)(struct nvif_chan *); + } push; + + struct { + u32 (*read_get)(struct nvif_chan *); + void (*push)(struct nvif_chan *, bool main, u64 addr, u32 size, + bool no_prefetch); + void (*kick)(struct nvif_chan *); + int (*post)(struct nvif_chan *, u32 gpptr, u32 pbptr); + u32 post_size; + } gpfifo; + + struct { + int (*release)(struct nvif_chan *, u64 addr, u32 data); + } sem; + } *func; + + struct { + struct nvif_map map; + } userd; + + struct { + struct nvif_map map; + u32 cur; + u32 max; + int free; + } gpfifo; + + struct { + struct nvif_map map; + u64 addr; + } sema; + + struct nvif_push push; + + struct nvif_user *usermode; + u32 doorbell_token; +}; + +int nvif_chan_dma_wait(struct nvif_chan *, u32 push_nr); + +void nvif_chan_gpfifo_ctor(const struct nvif_chan_func *, void *userd, void *gpfifo, u32 gpfifo_size, + void *push, u64 push_addr, u32 push_size, struct nvif_chan *); +int nvif_chan_gpfifo_wait(struct nvif_chan *, u32 gpfifo_nr, u32 push_nr); +void nvif_chan_gpfifo_push(struct nvif_chan *, u64 addr, u32 size, bool no_prefetch); +int nvif_chan_gpfifo_post(struct nvif_chan *); + +void nvif_chan506f_gpfifo_push(struct nvif_chan *, bool main, u64 addr, u32 size, bool no_prefetch); +void nvif_chan506f_gpfifo_kick(struct nvif_chan *); + +int nvif_chan906f_ctor_(const struct nvif_chan_func *, void *userd, void *gpfifo, u32 gpfifo_size, + void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr, + struct nvif_chan *); +u32 nvif_chan906f_read_get(struct nvif_chan *); +u32 nvif_chan906f_gpfifo_read_get(struct nvif_chan *); +int nvif_chan906f_gpfifo_post(struct nvif_chan *, u32 gpptr, u32 pbptr); + +int nvif_chan506f_ctor(struct nvif_chan *, void *userd, void *gpfifo, u32 gpfifo_size, + void *push, u64 push_addr, u32 push_size); +int nvif_chan906f_ctor(struct nvif_chan *, void *userd, void *gpfifo, u32 gpfifo_size, + void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr); +int nvif_chanc36f_ctor(struct nvif_chan *, void *userd, void *gpfifo, u32 gpfifo_size, + void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr, + struct nvif_user *usermode, u32 doorbell_token); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h index ea937fa7bc55..ea8267e0d8da 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h @@ -29,6 +29,8 @@ struct nv_device_info_v0 { #define NV_DEVICE_INFO_V0_TURING 0x0c #define NV_DEVICE_INFO_V0_AMPERE 0x0d #define NV_DEVICE_INFO_V0_ADA 0x0e +#define NV_DEVICE_INFO_V0_HOPPER 0x0f +#define NV_DEVICE_INFO_V0_BLACKWELL 0x10 __u8 family; __u8 pad06[2]; __u64 ram_size; diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 824e052dcc25..ff6823cb2cd8 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -57,12 +57,15 @@ #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 +#define BLACKWELL_INLINE_TO_MEMORY_A 0x0000cd40 #define NV04_DISP /* cl0046.h */ 0x00000046 #define VOLTA_USERMODE_A 0x0000c361 #define TURING_USERMODE_A 0x0000c461 #define AMPERE_USERMODE_A 0x0000c561 +#define HOPPER_USERMODE_A 0x0000c661 +#define BLACKWELL_USERMODE_A 0x0000c761 #define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069 #define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369 @@ -85,6 +88,9 @@ #define TURING_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c46f #define AMPERE_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c56f #define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f +#define HOPPER_CHANNEL_GPFIFO_A 0x0000c86f +#define BLACKWELL_CHANNEL_GPFIFO_A 0x0000c96f +#define BLACKWELL_CHANNEL_GPFIFO_B 0x0000ca6f #define NV50_DISP /* if0010.h */ 0x00005070 #define G82_DISP /* if0010.h */ 0x00008270 @@ -102,8 +108,10 @@ #define TU102_DISP /* if0010.h */ 0x0000c570 #define GA102_DISP /* if0010.h */ 0x0000c670 #define AD102_DISP /* if0010.h */ 0x0000c770 +#define GB202_DISP 0x0000ca70 #define GV100_DISP_CAPS 0x0000c373 +#define GB202_DISP_CAPS 0x0000ca73 #define NV31_MPEG 0x00003174 #define G82_MPEG 0x00008274 @@ -118,6 +126,7 @@ #define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a #define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a #define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a +#define GB202_DISP_CURSOR 0x0000ca7a #define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b #define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b @@ -128,6 +137,7 @@ #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b #define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b +#define GB202_DISP_WINDOW_IMM_CHANNEL_DMA 0x0000ca7b #define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c #define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c @@ -153,6 +163,7 @@ #define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d #define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d #define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d +#define GB202_DISP_CORE_CHANNEL_DMA 0x0000ca7d #define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e #define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e @@ -164,6 +175,7 @@ #define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e #define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e #define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e +#define GB202_DISP_WINDOW_CHANNEL_DMA 0x0000ca7e #define NV50_TESLA 0x00005097 #define G82_TESLA 0x00008297 @@ -189,16 +201,25 @@ #define TURING_A /* cl9097.h */ 0x0000c597 +#define AMPERE_A 0x0000c697 #define AMPERE_B /* cl9097.h */ 0x0000c797 #define ADA_A /* cl9097.h */ 0x0000c997 +#define HOPPER_A 0x0000cb97 + +#define BLACKWELL_A 0x0000cd97 +#define BLACKWELL_B 0x0000ce97 + #define NV74_BSP 0x000074b0 +#define NVB8B0_VIDEO_DECODER 0x0000b8b0 #define NVC4B0_VIDEO_DECODER 0x0000c4b0 #define NVC6B0_VIDEO_DECODER 0x0000c6b0 #define NVC7B0_VIDEO_DECODER 0x0000c7b0 #define NVC9B0_VIDEO_DECODER 0x0000c9b0 +#define NVCDB0_VIDEO_DECODER 0x0000cdb0 +#define NVCFB0_VIDEO_DECODER 0x0000cfb0 #define GT212_MSVLD 0x000085b1 #define IGT21A_MSVLD 0x000086b1 @@ -227,10 +248,14 @@ #define TURING_DMA_COPY_A 0x0000c5b5 #define AMPERE_DMA_COPY_A 0x0000c6b5 #define AMPERE_DMA_COPY_B 0x0000c7b5 +#define HOPPER_DMA_COPY_A 0x0000c8b5 +#define BLACKWELL_DMA_COPY_A 0x0000c9b5 +#define BLACKWELL_DMA_COPY_B 0x0000cab5 #define NVC4B7_VIDEO_ENCODER 0x0000c4b7 #define NVC7B7_VIDEO_ENCODER 0x0000c7b7 #define NVC9B7_VIDEO_ENCODER 0x0000c9b7 +#define NVCFB7_VIDEO_ENCODER 0x0000cfb7 #define FERMI_DECOMPRESS 0x000090b8 @@ -246,15 +271,25 @@ #define PASCAL_COMPUTE_B 0x0000c1c0 #define VOLTA_COMPUTE_A 0x0000c3c0 #define TURING_COMPUTE_A 0x0000c5c0 +#define AMPERE_COMPUTE_A 0x0000c6c0 #define AMPERE_COMPUTE_B 0x0000c7c0 #define ADA_COMPUTE_A 0x0000c9c0 +#define HOPPER_COMPUTE_A 0x0000cbc0 +#define BLACKWELL_COMPUTE_A 0x0000cdc0 +#define BLACKWELL_COMPUTE_B 0x0000cec0 #define NV74_CIPHER 0x000074c1 +#define NVB8D1_VIDEO_NVJPG 0x0000b8d1 #define NVC4D1_VIDEO_NVJPG 0x0000c4d1 #define NVC9D1_VIDEO_NVJPG 0x0000c9d1 +#define NVCDD1_VIDEO_NVJPG 0x0000cdd1 +#define NVCFD1_VIDEO_NVJPG 0x0000cfd1 +#define NVB8FA_VIDEO_OFA 0x0000b8fa #define NVC6FA_VIDEO_OFA 0x0000c6fa #define NVC7FA_VIDEO_OFA 0x0000c7fa #define NVC9FA_VIDEO_OFA 0x0000c9fa +#define NVCDFA_VIDEO_OFA 0x0000cdfa +#define NVCFFA_VIDEO_OFA 0x0000cffa #endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/object.h b/drivers/gpu/drm/nouveau/include/nvif/object.h index 8d205b6af46a..1b32dc701f61 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/object.h +++ b/drivers/gpu/drm/nouveau/include/nvif/object.h @@ -16,7 +16,7 @@ struct nvif_object { u32 handle; s32 oclass; void *priv; /*XXX: hack */ - struct { + struct nvif_map { void __iomem *ptr; u64 size; } map; diff --git a/drivers/gpu/drm/nouveau/include/nvif/push.h b/drivers/gpu/drm/nouveau/include/nvif/push.h index 6d3a8a3d2087..a493fababe3c 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/push.h +++ b/drivers/gpu/drm/nouveau/include/nvif/push.h @@ -31,6 +31,12 @@ struct nvif_push { void (*kick)(struct nvif_push *push); struct nvif_mem mem; + u64 addr; + + struct { + u32 get; + u32 max; + } hw; u32 *bgn; u32 *cur; @@ -41,7 +47,7 @@ struct nvif_push { static inline __must_check int PUSH_WAIT(struct nvif_push *push, u32 size) { - if (push->cur + size >= push->end) { + if (push->cur + size > push->end) { int ret = push->wait(push, size); if (ret) return ret; @@ -55,7 +61,11 @@ PUSH_WAIT(struct nvif_push *push, u32 size) static inline int PUSH_KICK(struct nvif_push *push) { - push->kick(push); + if (push->cur != push->bgn) { + push->kick(push); + push->bgn = push->cur; + } + return 0; } diff --git a/drivers/gpu/drm/nouveau/include/nvif/push906f.h b/drivers/gpu/drm/nouveau/include/nvif/push906f.h index cc2866bc8b0a..79df71de98d2 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/push906f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/push906f.h @@ -7,6 +7,7 @@ #ifndef PUSH906F_SUBC // Host methods #define PUSH906F_SUBC_NV906F 0 +#define PUSH906F_SUBC_NVC36F 0 // Twod #define PUSH906F_SUBC_NV902D 3 diff --git a/drivers/gpu/drm/nouveau/include/nvif/pushc97b.h b/drivers/gpu/drm/nouveau/include/nvif/pushc97b.h new file mode 100644 index 000000000000..c8d6b6319134 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/pushc97b.h @@ -0,0 +1,18 @@ +#ifndef __NVIF_PUSHC97B_H__ +#define __NVIF_PUSHC97B_H__ +#include <nvif/push.h> + +#include <nvhw/class/clc97b.h> + +#define PUSH_HDR(p,m,c) do { \ + PUSH_ASSERT(!((m) & ~DRF_SMASK(NVC97B_DMA_METHOD_OFFSET)), "mthd"); \ + PUSH_ASSERT(!((c) & ~DRF_MASK(NVC97B_DMA_METHOD_COUNT)), "size"); \ + PUSH_DATA__((p), NVDEF(NVC97B, DMA, OPCODE, METHOD) | \ + NVVAL(NVC97B, DMA, METHOD_COUNT, (c)) | \ + NVVAL(NVC97B, DMA, METHOD_OFFSET, (m) >> 2), \ + " mthd 0x%04x size %d - %s", (u32)(m), (u32)(c), __func__); \ +} while(0) + +#define PUSH_MTHD_HDR(p,s,m,c) PUSH_HDR(p,m,c) +#define PUSH_MTHD_INC 4:4 +#endif |