summaryrefslogtreecommitdiff
path: root/drivers/phy/rockchip
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/phy/rockchip')
-rw-r--r--drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c91
-rw-r--r--drivers/phy/rockchip/phy-rockchip-naneng-combphy.c15
-rw-r--r--drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c27
3 files changed, 118 insertions, 15 deletions
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
index d5b1a4e2f7d3..30d5e5ddff4a 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
@@ -99,10 +99,30 @@
#define VOD_MID_RANGE 0x3
#define VOD_BIG_RANGE 0x7
#define VOD_MAX_RANGE 0xf
+/* Analog Register Part: reg18 */
+#define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6)
+#define LANE0_PRE_EMPHASIS_ENABLE BIT(6)
+#define LANE0_PRE_EMPHASIS_DISABLE 0
+#define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5)
+#define LANE1_PRE_EMPHASIS_ENABLE BIT(5)
+#define LANE1_PRE_EMPHASIS_DISABLE 0
+/* Analog Register Part: reg19 */
+#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
+#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
/* Analog Register Part: reg1E */
#define PLL_MODE_SEL_MASK GENMASK(6, 5)
#define PLL_MODE_SEL_LVDS_MODE 0
#define PLL_MODE_SEL_MIPI_MODE BIT(5)
+/* Analog Register Part: reg20 */
+#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
+#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
+/* Analog Register Part: reg21 */
+#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
+#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
+#define PRE_EMPHASIS_MIN_RANGE 0x0
+#define PRE_EMPHASIS_MID_RANGE 0x1
+#define PRE_EMPHASIS_MAX_RANGE 0x2
+#define PRE_EMPHASIS_RESERVED_RANGE 0x3
/* Digital Register Part: reg00 */
#define REG_DIG_RSTN_MASK BIT(0)
#define REG_DIG_RSTN_NORMAL BIT(0)
@@ -193,6 +213,7 @@
enum phy_max_rate {
MAX_1GHZ,
+ MAX_1_5GHZ,
MAX_2_5GHZ,
};
@@ -200,6 +221,7 @@ struct inno_video_phy_plat_data {
const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
const unsigned int num_timings;
enum phy_max_rate max_rate;
+ unsigned int max_lanes;
};
struct inno_dsidphy {
@@ -259,6 +281,24 @@ struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = {
};
static const
+struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = {
+ { 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
+ { 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
+ { 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
+ { 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
+ { 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
+ { 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
+ { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
+ { 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
+ { 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
+ { 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
+ {1000, 0x05, 0x08, 0x20, 0x09, 0x30},
+ {1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
+ {1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
+ {1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
+};
+
+static const
struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = {
{ 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02},
{ 150000000, 0x02, 0x7f, 0x16, 0x03, 0x02},
@@ -372,6 +412,7 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
unsigned int i;
+ u32 val;
timings = inno->pdata->inno_mipi_dphy_timing_table;
@@ -393,6 +434,23 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
CLOCK_LANE_VOD_RANGE_SET_MASK,
CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
+ } else if (inno->pdata->max_rate == MAX_1_5GHZ) {
+ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18,
+ LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE);
+ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18,
+ LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE);
+ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19,
+ PRE_EMPHASIS_RANGE_SET_MASK,
+ PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
+ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a,
+ LANE0_PRE_EMPHASIS_RANGE_SET_MASK,
+ LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
+ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b,
+ LANE1_PRE_EMPHASIS_RANGE_SET_MASK,
+ LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
+ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
+ CLOCK_LANE_VOD_RANGE_SET_MASK,
+ CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
}
/* Enable PLL and LDO */
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
@@ -518,10 +576,25 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
T_TA_WAIT_CNT(ta_wait));
}
- /* Enable all lanes on analog part */
+ /* Enable lanes on analog part */
+ switch (inno->pdata->max_lanes) {
+ case 1:
+ val = LANE_EN_0;
+ break;
+ case 2:
+ val = LANE_EN_0 | LANE_EN_1;
+ break;
+ case 3:
+ val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2;
+ break;
+ case 4:
+ default:
+ val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2 | LANE_EN_3;
+ break;
+ }
+
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
- LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
- LANE_EN_1 | LANE_EN_0);
+ LANE_EN_MASK, LANE_EN_CK | val);
}
static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
@@ -680,12 +753,21 @@ static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = {
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz,
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz),
.max_rate = MAX_1GHZ,
+ .max_lanes = 4,
+};
+
+static const struct inno_video_phy_plat_data max_1_5ghz_video_phy_plat_data = {
+ .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz,
+ .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz),
+ .max_rate = MAX_1_5GHZ,
+ .max_lanes = 2,
};
static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = {
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz,
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz),
.max_rate = MAX_2_5GHZ,
+ .max_lanes = 4,
};
static int inno_dsidphy_probe(struct platform_device *pdev)
@@ -768,6 +850,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = {
.compatible = "rockchip,rk3368-dsi-dphy",
.data = &max_1ghz_video_phy_plat_data,
}, {
+ .compatible = "rockchip,rk3506-dsi-dphy",
+ .data = &max_1_5ghz_video_phy_plat_data,
+ }, {
.compatible = "rockchip,rk3568-dsi-dphy",
.data = &max_2_5ghz_video_phy_plat_data,
}, {
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index a3ef19807b9e..7f8fc8e6d489 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -21,6 +21,9 @@
#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
/* RK3528 COMBO PHY REG */
+#define RK3528_PHYREG5 0x14
+#define RK3528_PHYREG5_GATE_TX_PCK_SEL BIT(3)
+#define RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF BIT(3)
#define RK3528_PHYREG6 0x18
#define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
#define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
@@ -103,6 +106,10 @@
#define RK3568_PHYREG18 0x44
#define RK3568_PHYREG18_PLL_LOOP 0x32
+#define RK3568_PHYREG30 0x74
+#define RK3568_PHYREG30_GATE_TX_PCK_SEL BIT(7)
+#define RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF BIT(7)
+
#define RK3568_PHYREG32 0x7C
#define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4)
#define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
@@ -504,6 +511,10 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
case REF_CLOCK_100MHz:
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->type == PHY_TYPE_PCIE) {
+ /* Gate_tx_pck_sel length select for L1ss support */
+ rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL,
+ RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF, RK3528_PHYREG5);
+
/* PLL KVCO tuning fine */
val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
@@ -657,6 +668,10 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
case REF_CLOCK_100MHz:
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->type == PHY_TYPE_PCIE) {
+ /* Gate_tx_pck_sel length select for L1ss support */
+ rockchip_combphy_updatel(priv, RK3568_PHYREG30_GATE_TX_PCK_SEL,
+ RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF,
+ RK3568_PHYREG30);
/* PLL KVCO tuning fine */
val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
RK3568_PHYREG33_PLL_KVCO_VALUE);
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 01bbf668e05e..29de2f7bdae8 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -500,9 +500,7 @@ static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(0043), 0x00),
REG_SEQ0(CMN_REG(0044), 0x46),
REG_SEQ0(CMN_REG(0045), 0x24),
- REG_SEQ0(CMN_REG(0046), 0xff),
REG_SEQ0(CMN_REG(0047), 0x00),
- REG_SEQ0(CMN_REG(0048), 0x44),
REG_SEQ0(CMN_REG(0049), 0xfa),
REG_SEQ0(CMN_REG(004a), 0x08),
REG_SEQ0(CMN_REG(004b), 0x00),
@@ -575,6 +573,8 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(0034), 0x00),
REG_SEQ0(CMN_REG(003d), 0x40),
REG_SEQ0(CMN_REG(0042), 0x78),
+ REG_SEQ0(CMN_REG(0046), 0xdd),
+ REG_SEQ0(CMN_REG(0048), 0x11),
REG_SEQ0(CMN_REG(004e), 0x34),
REG_SEQ0(CMN_REG(005c), 0x25),
REG_SEQ0(CMN_REG(005e), 0x4f),
@@ -668,13 +668,9 @@ static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
REG_SEQ0(LANE_REG(0312), 0x00),
- REG_SEQ0(LANE_REG(031e), 0x00),
REG_SEQ0(LANE_REG(0412), 0x00),
- REG_SEQ0(LANE_REG(041e), 0x00),
REG_SEQ0(LANE_REG(0512), 0x00),
- REG_SEQ0(LANE_REG(051e), 0x00),
REG_SEQ0(LANE_REG(0612), 0x00),
- REG_SEQ0(LANE_REG(061e), 0x08),
REG_SEQ0(LANE_REG(0303), 0x2f),
REG_SEQ0(LANE_REG(0403), 0x2f),
REG_SEQ0(LANE_REG(0503), 0x2f),
@@ -687,6 +683,11 @@ static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
REG_SEQ0(LANE_REG(0406), 0x1c),
REG_SEQ0(LANE_REG(0506), 0x1c),
REG_SEQ0(LANE_REG(0606), 0x1c),
+ /* Keep Inter-Pair Skew in the limits */
+ REG_SEQ0(LANE_REG(031e), 0x02),
+ REG_SEQ0(LANE_REG(041e), 0x02),
+ REG_SEQ0(LANE_REG(051e), 0x02),
+ REG_SEQ0(LANE_REG(061e), 0x0a),
};
static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = {
@@ -1037,7 +1038,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
ret = rk_hdptx_post_enable_pll(hdptx);
if (!ret)
- hdptx->hw_rate = hdptx->hdmi_cfg.tmds_char_rate;
+ hdptx->hw_rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8,
+ hdptx->hdmi_cfg.bpc);
return ret;
}
@@ -1895,19 +1897,20 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
* hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with
* a different rate argument.
*/
- return hdptx->hdmi_cfg.tmds_char_rate;
+ return DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8, hdptx->hdmi_cfg.bpc);
}
static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+ unsigned long long tmds_rate = DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi_cfg.bpc, 8);
/* Revert any unlikely TMDS char rate change since round_rate() */
- if (hdptx->hdmi_cfg.tmds_char_rate != rate) {
- dev_warn(hdptx->dev, "Reverting unexpected rate change from %lu to %llu\n",
- rate, hdptx->hdmi_cfg.tmds_char_rate);
- hdptx->hdmi_cfg.tmds_char_rate = rate;
+ if (hdptx->hdmi_cfg.tmds_char_rate != tmds_rate) {
+ dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu\n",
+ tmds_rate, hdptx->hdmi_cfg.tmds_char_rate);
+ hdptx->hdmi_cfg.tmds_char_rate = tmds_rate;
}
/*
generated by cgit (git 2.34.1) at 2025-12-11 05:42:48 +0000