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Diffstat (limited to 'include/dt-bindings/clock/r9a08g045-cpg.h')
-rw-r--r--include/dt-bindings/clock/r9a08g045-cpg.h71
1 files changed, 0 insertions, 71 deletions
diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h
index 311521fe4b59..410725b778a8 100644
--- a/include/dt-bindings/clock/r9a08g045-cpg.h
+++ b/include/dt-bindings/clock/r9a08g045-cpg.h
@@ -239,75 +239,4 @@
#define R9A08G045_I3C_PRESETN 92
#define R9A08G045_VBAT_BRESETN 93
-/* Power domain IDs. */
-#define R9A08G045_PD_ALWAYS_ON 0
-#define R9A08G045_PD_GIC 1
-#define R9A08G045_PD_IA55 2
-#define R9A08G045_PD_MHU 3
-#define R9A08G045_PD_CORESIGHT 4
-#define R9A08G045_PD_SYC 5
-#define R9A08G045_PD_DMAC 6
-#define R9A08G045_PD_GTM0 7
-#define R9A08G045_PD_GTM1 8
-#define R9A08G045_PD_GTM2 9
-#define R9A08G045_PD_GTM3 10
-#define R9A08G045_PD_GTM4 11
-#define R9A08G045_PD_GTM5 12
-#define R9A08G045_PD_GTM6 13
-#define R9A08G045_PD_GTM7 14
-#define R9A08G045_PD_MTU 15
-#define R9A08G045_PD_POE3 16
-#define R9A08G045_PD_GPT 17
-#define R9A08G045_PD_POEGA 18
-#define R9A08G045_PD_POEGB 19
-#define R9A08G045_PD_POEGC 20
-#define R9A08G045_PD_POEGD 21
-#define R9A08G045_PD_WDT0 22
-#define R9A08G045_PD_XSPI 23
-#define R9A08G045_PD_SDHI0 24
-#define R9A08G045_PD_SDHI1 25
-#define R9A08G045_PD_SDHI2 26
-#define R9A08G045_PD_SSI0 27
-#define R9A08G045_PD_SSI1 28
-#define R9A08G045_PD_SSI2 29
-#define R9A08G045_PD_SSI3 30
-#define R9A08G045_PD_SRC 31
-#define R9A08G045_PD_USB0 32
-#define R9A08G045_PD_USB1 33
-#define R9A08G045_PD_USB_PHY 34
-#define R9A08G045_PD_ETHER0 35
-#define R9A08G045_PD_ETHER1 36
-#define R9A08G045_PD_I2C0 37
-#define R9A08G045_PD_I2C1 38
-#define R9A08G045_PD_I2C2 39
-#define R9A08G045_PD_I2C3 40
-#define R9A08G045_PD_SCIF0 41
-#define R9A08G045_PD_SCIF1 42
-#define R9A08G045_PD_SCIF2 43
-#define R9A08G045_PD_SCIF3 44
-#define R9A08G045_PD_SCIF4 45
-#define R9A08G045_PD_SCIF5 46
-#define R9A08G045_PD_SCI0 47
-#define R9A08G045_PD_SCI1 48
-#define R9A08G045_PD_IRDA 49
-#define R9A08G045_PD_RSPI0 50
-#define R9A08G045_PD_RSPI1 51
-#define R9A08G045_PD_RSPI2 52
-#define R9A08G045_PD_RSPI3 53
-#define R9A08G045_PD_RSPI4 54
-#define R9A08G045_PD_CANFD 55
-#define R9A08G045_PD_ADC 56
-#define R9A08G045_PD_TSU 57
-#define R9A08G045_PD_OCTA 58
-#define R9A08G045_PD_PDM 59
-#define R9A08G045_PD_PCI 60
-#define R9A08G045_PD_SPDIF 61
-#define R9A08G045_PD_I3C 62
-#define R9A08G045_PD_VBAT 63
-
-#define R9A08G045_PD_DDR 64
-#define R9A08G045_PD_TZCDDR 65
-#define R9A08G045_PD_OTFDE_DDR 66
-#define R9A08G045_PD_RTC 67
-
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */