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2018-09-14ARM: dts: aspeed: quanta-q71l: Enable adc & ibt nodesPatrick Venture
This machine uses the ADC and iBT devices. Signed-off-by: Patrick Venture <venture@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-09-14ARM: dts: aspeed: quanta-q71l: Add four PSUsPatrick Venture
Enable the four PSUs via generic PMBUS. Signed-off-by: Patrick Venture <venture@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-09-14ARM: dts: aspeed: quanta-q71l: add aliases for i2cPatrick Venture
Provide aliases to each i2c bus per labels added for each PCIe slot, etc, that are downstream beyond a mux. Signed-off-by: Patrick Venture <venture@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-09-14ARM: dts: aspeed: Fix I2C bus warningsRob Herring
dtc has new checks for I2C buses. The ASpeed dts files have a node named 'i2c' which causes a false positive warning. As the node is a 'simple-bus', correct the node name to be 'bus' to fix the warnings. arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-romulus.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-ast2500-evb.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-zaius.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: linux-aspeed@lists.ozlabs.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-09-13ARM: dts: bcm: Fix SPI bus warningsRob Herring
dtc has new checks for SPI buses. Fix the warnings in node names. arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dtb: Warning (spi_bus_bridge): /axi@18000000/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958525er.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958525xmc.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958622hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958625hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm988312hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-09-13arm64: dts: broadcom: Fix I2C and SPI bus warningsRob Herring
dtc has new checks for I2C and SPI buses. Fix the warnings in node names and unit-addresses. arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27" arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27" arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@180000: node name for SPI buses should be 'spi' arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@190000: node name for SPI buses should be 'spi' Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-09-13Merge tag 'tags/bcm2835-dt-next-2018-09-09' into devicetree/nextFlorian Fainelli
This pull request brings in a board DT for the Raspberry Pi Compute Module 3, its I/O board and enables the Ethernet LEDs for the RPi 3B+. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-09-13ARM: dts: NSP: Wire up switch interruptsFlorian Fainelli
The Switch Register Access Block (SRAB) has one interrupt for link state change on each ports (0-5, 7-8) a PHY interrupt, timestamping interrupt and sleep timer interrupts for each management ports (5,7,8). Wire those up so we can utilize them to speed up link resolution. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-09-13dt-bindings: net: dsa: Document B53 SRAB interrupts and registersFlorian Fainelli
Document the Broadcom roboswitch Switch Register Access Block interrupt lines and additional register base addresses for port mux configuration and SGMII status/configuration registers. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org>
2018-09-13ARM: dts: NSP: Enable SFP on bcm958625hrFlorian Fainelli
Enable the SFP connected to port 5 of the switch and wire up all GPIOs to the SFP cage. Because of a hardware limitation of the i2c controller on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to work, we use the i2c-gpio interface instead, which does not have that limitation. This allows us to read the SFP module EEPROM, which would not be possible otherwise since it exceeds that size during a single read transfer. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
2018-09-13arm64: dts: meson: Switch simple-mfd and syscon orderNeil Armstrong
The order between "syscon" and "simple-mfd" is important because in these particular cases, the node needs to be first a "simple-mfd" to expose it's sub-nodes, and later on a "syscon" to permit other nodes to access this register space through the "syscon" mechanism. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-13arm64: dts: r8a77965: add FDP1 device nodesHoan Nguyen An
The r8a77965 has a single FDP1 instance. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: draak: Sort device nodesGeert Uytterhoeven
- Device nodes with unit addresses are sorted by unit address, - Device nodes without unit addresses and references are sorted alphabetically. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: enable SDR104 on R-Car Gen3Wolfram Sang
Successfully tested on H3 ES1.0 and ES2.0, M3-W ES1.0, and M3-N ES1.0. Even previously stubborn cards work fine. Transfer rates were >60MB/s. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77990: Add SYS-DMAC device nodesTakeshi Kihara
This patch adds SYS-DMAC{0,1,2} device nodes for the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77990: Add I2C device nodesTakeshi Kihara
Add device nodes for I2C ch[0-7] to R-Car E3 R8A77990 device tree. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77990: Add VIN and CSI-2 device nodesKoji Matsuoka
Add device nodes for VIN4, VIN5 and CSI40 to R-Car E3 R8A77990 device tree. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> [simon: sorted nodes by bus address, then IP block] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77990: Add all MSIOF nodesGeert Uytterhoeven
Add the device nodes for all MSIOF SPI controllers, incl. clocks, power domains, and resets properties. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a7795: Move arm_cc630p nodeGeert Uytterhoeven
To preserve by-address-per-group sort order. Fixes: 0f6d237cafda2e06 ("arm64: dts: renesas: r8a7795: add ccree to device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77990: Add BRG support to SCIF2Takeshi Kihara
Add the device node for the external SCIF_CLK, and describe the clock inputs for the Baud Rate Generator for External Clock (BRG) for SCIF2, which can increase serial clock accuracy. The presence of the SCIF_CLK crystal and its clock frequency depend on the actual board. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Enhance patch description] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77990: Use CPG/MSSR and SYSC binding definitionsGeert Uytterhoeven
Use the SoC-specific CPG/MSSR include file to allow future use of R8A77990_CLK_* symbols. Replace the hardcoded power domain indices by R8A77990_PD_* symbols. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: salvator-xs: Improve SATA switch settings commentsGeert Uytterhoeven
The comments describing the non-default switch settings to use SATA are confusing: 'Off' refers to the switch position, not to the MD12 logic value, while the parentheses suggest otherwise. Rephrase to fix this. Fixes: bec000784d5bb571 ("arm64: dts: renesas: salvator-xs: enable SATA") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77965: Fix clock/reset for usb2_phy1Geert Uytterhoeven
usb2_phy1 accidentally uses the same clock/reset as usb2_phy0. Fixes: b5857630a829a8d5 ("arm64: dts: renesas: r8a77965: add usb2_phy nodes") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77965: Fix HS-USB compatibleGeert Uytterhoeven
Should be "renesas,usbhs-r8a77965", not "renesas,usbhs-r8a7796". Fixes: a06e8af801760a98 ("arm64: dts: renesas: r8a77965: add HS-USB node") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77965: Move timer nodeGeert Uytterhoeven
To preserve alphabetical sort order. Fixes: 4c529600eef0a6b7 ("arm64: dts: renesas: r8a77965: Add R-Car Gen3 thermal support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: v3hsk: Move lvds0 nodeGeert Uytterhoeven
To preserve alphabetical sort order. Fixes: 4edac426aff11a37 ("arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: Fix whitespace around assignmentsGeert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> [simon: updated for a few new cases] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77965: m3nulcb-kf: Initial device treeEugeniu Rosca
This is based on the existing KF device tree sources: $ ls -1 arch/arm64/boot/dts/renesas/*-kf.dts arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: condor: add PCIe supportSergei Shtylyov
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor board. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a77980: add PCIe supportSergei Shtylyov
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device tree. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add USB3.0 device nodesBiju Das
Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add USB-DMAC and HSUSB device nodesBiju Das
Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add USB2.0 phy and host(EHCI/OHCI) device nodesBiju Das
Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add FCPF and FCPV instancesFabrizio Castro
Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly to what was done for the r8a7796 with commit 41dbbf0c5b4e ("arm64: dts: r8a7796: Add FCPF and FCPV instances"), commit 69490bc9665d ("arm64: dts: renesas: r8a7796: Point FDP1 via FCPF to IPMMU-VI0"), and commit cef942d0bd89 ("arm64: dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0"). Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add audio supportBiju Das
Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1). This work is based on similar work done on the R8A7796 SoC by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add PWM device nodesFabrizio Castro
This patch adds PWM[0123456] device nodes to the RZ/G2M (a.k.a R8A774A1) device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU coresBiju Das
This patch adds definitions for L2 cache for the Cortex-A53 CPU cores (512 KiB in size, organized as 32 KiB x 16 ways), adds Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57 + 4 x Cortex-A53), and finally enables the performance monitor unit for the Cortex-A53 cores on the R8A774A1 SoC. Based on work done for r8a7796 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add all MSIOF nodesBiju Das
Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC. Based on several similar patches of the R8A7796 device tree by Geert Uytterhoeven <geert+renesas@glider.be> and Simon Horman <horms+renesas@verge.net.au>. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add IPMMU device nodesFabrizio Castro
Add r8a774a1 IPMMU nodes. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add RZ/G2M thermal supportBiju Das
Add thermal support for R8A774A1 (RZ/G2M) SoC. Based on the work done for r8a7796 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add I2C and IIC-DVFS supportBiju Das
Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS) devices nodes to the r8a774a1 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add SDHI nodesFabrizio Castro
Add SDHI nodes to the DT of the r8a774a1 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add GPIO device nodesFabrizio Castro
Add GPIO device nodes to the DT of the r8a774a1 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add pinctrl device nodeFabrizio Castro
This patch adds pinctrl device node for R8A774A1 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add RWDT nodeBiju Das
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas RZ/G2M (r8a774a1) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add Ethernet AVB nodeFabrizio Castro
This patch adds the SoC specific part of the Ethernet AVB device tree node. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add INTC-EX device nodeBiju Das
Add support for the Interrupt Controller for External Devices (INTC-EX) on RZ/G2M. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodesFabrizio Castro
Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports, incl. clocks, power domains and DMAs. According to the HW user manual, SCIF[015] and HSCIF[012] are connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and HSCIF[34] are connected to SYS-DMAC0. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodesBiju Das
Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-13arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI supportSergei Shtylyov
Define the Condor/V3HSK board dependent parts of the DU and LVDS device nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and Analog Devices ADV7511W HDMI transmitter... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit (git 2.34.1) at 2025-09-14 01:55:09 +0000