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2014-11-23ARM: imx53: clk: add ARM clockLucas Stach
The ARM clock is a virtual clock feeding the ARM partition of the SoC. It controls multiple other clocks to ensure the right sequencing when cpufreq changes the CPU clock rate. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: add CPU clock typeLucas Stach
This implements a virtual clock used to abstract away all the steps needed in order to change the ARM clock, so we don't have to push all this clock handling into the cpufreq driver. While it will be used for i.MX53 at first it is generic enough to be used on i.MX6 later on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx5: add step clock, used when reprogramming PLL1Lucas Stach
This is the bypass clock used to feed the ARM partition while we reprogram PLL1 to another rate. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: add enet init for i.mx6sxFugang Duan
Add enet init for i.mx6sx: - Add phy ar8031 fixup - Set enet clock source from internal PLL Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: vf610: Add ARM Global Timer clocksource optionStefan Agner
Add the ARM Global Timer as clocksource/scheduler clock option and use it as default scheduler clock. This leaves the PIT timer for other users e.g. the secondary Cortex-M4 core. Also, the Global Timer has double the precission (running at pheripheral clock compared to IPG clock) and a 64-bit incrementing counter register. We still keep the PIT timer as an secondary option in case the ARM Global Timer is not available. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: add anatop settings for LPDDR2 when enter DSM modeAnson Huang
For LPDDR2 platform, no need to enable weak2P5 in DSM mode, it can be pulled down to save power(~0.65mW). And per design team's recommendation, we should disconnect VDDHIGH and SNVS in DSM mode on i.MX6SL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: replace cpu type check with ddr type checkAnson Huang
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3, we used cpu type to decide how to do these settings in suspend before which is NOT flexible, take i.MX6SL for example, although it has LPDDR2 on EVK board, but users can also use DDR3 on other boards, so it is better to read the DDR type from MMDC then decide how to do related settings. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-22ARM: dts: rockchip: temporarily disable smp on rk3288Heiko Stuebner
Stock firmware on rk3288 does not initizalize the CNTVOFF registers of the architected timer correctly. This introduces issues with the newly added SMP support for rk3288, resulting in rcu stalls due to differing timer values per core. There exist preliminary and tested patches for u-boot for this problem, but there are a minority of boards using other bootloaders like coreboot. There also is currently a second solution for miss-initialized architected timers in the works: - clocksource: arch_timer: Fix code to use physical timers when requested - clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers Therefore disable smp on rk3288 again till these are finalized, also allowing coreboot-based boards to boot again. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-22ARM: dts: add missing clock to MFC device for exynos4Marek Szyprowski
sclk_mfc is required for MFC device since commit 0c2272170d78f826f6e97f99fb8a67fc17feef07 ("media: s5p-mfc: rename special clock to sclk_mfc"), so add it to exynos4 dts. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Specify audio clock parents and rates for exynos4412-odroid-commonSylwester Nawrocki
This ensures the core and the audio subsystem clocks are configured properly, as expected by the sound machine driver. These bits are missing to obtain proper audio sample rates in kernel v3.17, where audio support for Odroid X2/U3 was first added. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Add trackpad to exynos5250-springAndreas Faerber
The HP Chromebook 11 uses an Atmel maXTouch as trackpad. The keymap was found by trial-and-error. Signed-off-by: Andreas Faerber <afaerber@suse.de> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Add temperature sensor to exynos5250-springAndreas Faerber
Spotted in the Chrome OS 3.8 based device tree. Needs CONFIG_SENSORS_LM90. Signed-off-by: Andreas Faerber <afaerber@suse.de> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Add usb3503 pinctrl to exynos5250-springAndreas Faerber
Reported-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Andreas Faerber <afaerber@suse.de> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Add max77693-haptic node for exynos4412-trats2Jaewon Kim
This patch adds max77693-haptic node to support for haptic motor driver. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: add pwm node for exynos4412-trats2Jaewon Kim
This patch add PWM(Pulse Width Modulation) node and handle to use pwm property. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Specify default clocks for Exynos4 camera devicesSylwester Nawrocki
Specify the default mux and divider clocks in device tree to ensure the FIMC devices on Trats, Trats2, Universal_c210 and Odroid X2/U3 boards are clocked from recommended clock source and with maximum supported frequency. For Trats2 also the MIPI-CSIS and the camera sensor clocks are configured, the 'clock-frequency' property is deprecated in favour of 'assigned-clock-rates' property. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: EXYNOS: move restart code into pmu driverPankaj Dubey
Let's register restart handler from PMU driver for restart functionality. So that we can remove restart hooks from machine specific file, and thus moving ahead when PMU moved to driver folder, this functionality can be reused for ARM64 based Exynos SoC's. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22clk: exynos5440: move restart code into clock driverPankaj Dubey
Let's register restart handler for Exynos5440 from it's clock driver for restart functionality. So that we can cleanup restart hooks from machine specific file. CC: Sylwester Nawrocki <s.nawrocki@samsung.com> CC: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: EXYNOS: add exynos3250 PMU supportBartlomiej Zolnierkiewicz
This patch prepares the PMU code for the future: - suspend/resume (S2R) support - cpuidle AFTR/W-AFTR modes support on Exynos3250. Cc: Vikas Sajjan <vikas.sajjan@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> [kgene.kim@samsung.com: fixed coding style] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Enable TMU support for exynos4412-trats2Lukasz Majewski
This patch enables support for TMU at Exynos4412 based Trats2 board. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Device tree node definition for TMU on exynos4x12Lukasz Majewski
The TMU device tree node definition for Exynos4x12 family of SoCs. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22arm: mvebu: add .dts file for Synology DS414Arnaud Ebalard
Synology DS414 is a 4-bay NAS powered by a Marvell Armada XP (mv78230 dual-core @1.33Ghz). It is very similar on many aspects to previous 4-bay synology models based on Marvell kirkwood SoC. Here is a short summary of the device: - 1GB RAM - Boot on SPI flash (64Mbit Micron N25Q064) - 2 GbE interfaces (Armada MAC connected to two Marvell 88E1512 PHY via RGMII) - 1 front USB 2.0 ports (directly handled by the Armada 370) - 2 rear USB 3.0 ports (handled by an EtronTech EJ168A XHCI controller on the PCIe bus) - 4 internal SATA ports handled by a Marvell 88SX7042 SATA-II controller on the PCIe bus) - Seiko S-35390A I2C RTC chip - UART0 providing serial console - UART1 used for poweroff (connected to a Microchip PIC16F883) Additional note: the front LEDs the and the two fans are not directly connected to the SoC and under its control. The former are presumably driven by the SATA controller, the latter by the PIC. [ jac: fixed up s/ge[01]_rgmii_pins/pmx_ge[01]_rgmii/ to match armada-xp.dtsi ] Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/5b678d6d1f2f42f4bf0d087878b9d8024d463ea7.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: add .dts file for Synology DS213jArnaud Ebalard
Synology DS213j is a 2-bay NAS powered by a Marvell Armada 370 (88F6710 @1.2Ghz). It is very similar on many aspects to previous 2-bay synology models based on Marvell kirkwood SoC. Here is a short summary of the device: - 512MB RAM - boot on SPI flash (64Mbit Micron N25Q064) - 1 GbE interface (Armada MAC connected to a Marvell 88E1512 PHY via SGMII) - 2 rear USB 2.0 ports (directly handled by the Armada 370) - 2 internal SATA ports handled by the Armada 370: 2 GPIO for presence, 2 for powering them - two front amber LED (disk1, disk2) controlled by the SoC - Seiko S-35390A I2C RTC chip - UART0 providing serial console - UART1 used for poweroff (connected to a TI MSP430F2111) - Fan handled via 4 GPIO (3 for speed, 1 for alarm) Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/20f1a03897df1d825b62abdd525e588a8e39b3ec.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: define and use common Armada XP SPI pinctrl settingArnaud Ebalard
This patch defines common Armada XP pinctrl settings in armada-xp.dtsi for the supported SPI interface (MPP36-39) and use it as default for Armada XP spi interface. That being done, it removes the now redundant definitions in armada-xp-axpwifiap.dts. Note: this patch has the potential to break out-of-tree users w/o specific pinctrl settings for their spi interfaces if the default above does not match their config (i.e. if they do not use CS0). Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/d404b7abd80ee5a0fd8e8d3586d33cd37740d589.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: define and use common Armada XP UART2/3 pinctrl settingsArnaud Ebalard
This patch defines common Armada XP pinctrl settings for uart2 and uart3 interfaces (uart0 and uart1 rx/tx do not rely on MPP): uart2: MPP42-43 as default uart3: MPP44-45 as default Suggested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/fd51c080c7139a67ec01df8d797f1e88ce557796.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: define and use common Armada 370 UART pinctrl settingsArnaud Ebalard
This patch defines common Armada 370 pinctrl settings for uart0 and uart1 interfaces: uart0: MPP0-1 as default uart1: MPP41-42 as default Note: this patch has the potential to break out-of-tree users w/o specific pinctrl settings for their uart interfaces if the default above does not match their config. Suggested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/31412e57955c98bc9cc47b70726b5072af945cc3.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: define and use common Armada 370 SPI pinctrl settingsArnaud Ebalard
This patch defines common Armada 370 pinctrl settings for spi0 and spi1 interfaces: spi0: MPP33-36 as default, MPP32,63-65 as available alternate config spi1: MPP49-52 as default Currently, the Armada 370 DB .dts file has no explicit pinctrl info for the spi0 interface used to access the flash on the board. The patch fixes that by also adding explicit pinctrl info (MPP32,63-65) for this SPI interface. Note: this patch has the potential to break out-of-tree users w/o specific pinctrl settings for their spi interfaces if the default above does not match their config. Suggested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/1e812eb63b37718e273463e22e4d7512f8f0b624.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: move Armada 370/XP pinctrl node definition armada-370-xp.dtsiArnaud Ebalard
What was done by Sebastian in 264a05e19bf5 ("ARM: mvebu: armada-xp: Add node alias to pinctrl and add base address") and 01c434225ee6 ("ARM: mvebu: armada-xp: Use pinctrl node alias") can also be done for Armada 370, i.e. - Rename Armada 370 pinctrl node to pin-ctrl with its address encoded - Add a node alias to access the pinctrl node easily. - use the newly available alias in existing Armada 370 .dts files We can even go a bit further by putting the pinctrl node definition in armada-370-xp.dtsi, with only its reg property defined. This allows us to then also use the newly defined node alias in armada-xp.dtsi, armada-370.dtsi. Suggested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Suggested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/b54eb45e5242728aace3ce8aef2eae4251f8dea3.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: use recently introduced uart label for stdout-pathArnaud Ebalard
Now that labels for uartX are available in Marvell Armada .dtsi files, this patch replaces the "/soc/internal-regs/serial@12000" found in armada-xp-lenovo-ix4-300d.dts file for stdout-path property by the more concise &uart0. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Suggested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/d1a883510e01f7f212a385e826dccbef903fae42.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: add uartX labels for Armada SoC serial nodesArnaud Ebalard
This patch adds uartX labels for Armada SoC serial nodes. This is a preliminary work to be able to easily reference the serial lines in Device Tree files. One expected use is when providing stdout-path property for barebox. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/0683d1a823fe9b75849f3dafcf1cf6ee291cdca6.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: fix vendor prefix typo in kirkwood-synology.dtsiArnaud Ebalard
As reported by Andrew, the vendor prefix for Seiko Instruments, Inc. S-35390A I2C RTC chip in kirkwood-synology.dtsi has a typo (ssi instead of sii). This patches fixes it. Note: i2c devices ignore the optional vendor prefix, which explains why it worked with the typo and also why there is no backward compatibility issues with the fix. Reported-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/0444140a267d982c3e5f5f2b7b5f2dc41d010e2a.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: fix ordering in Armada 370 .dtsiUwe Kleine-König
Commit a095b1c78a35 ("ARM: mvebu: sort DT nodes by address") missed placing the system-controller in the correct order. Fixes: a095b1c78a35 ("ARM: mvebu: sort DT nodes by address") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/20141114204333.GS27002@pengutronix.de Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-21Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller
Conflicts: drivers/net/ieee802154/fakehard.c A bug fix went into 'net' for ieee802154/fakehard.c, which is removed in 'net-next'. Add build fix into the merge from Stephen Rothwell in openvswitch, the logging macros take a new initial 'log' argument, a new call was added in 'net' so when we merge that in here we have to explicitly add the new 'log' arg to it else the build fails. Signed-off-by: David S. Miller <davem@davemloft.net>
2014-11-22ARM: mvebu: add MTD_BLOCK to mvebu_v7_defconfigThomas Petazzoni
Since many (most?) mvebu platforms have NAND or SPI flashes, it makes sense to have CONFIG_MTD_BLOCK=y in mvebu_v7_defconfig. The vast majority of the other ARM defconfigs have it enabled, including mvebu_v5_defconfig. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1415873489-22446-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: adjust ethernet aliases according to U-Boot requirements for A38xMarcin Wojtas
In order to update MAC address entries in the ethernet nodes in Device Tree both mainline U-Boot and Barebox bootloaders accept the same format of aliases, which is 'ethernetX', where X stands for an interface number. Other platforms in the mainline Linux, that comprise ethernet references in '/aliases' node (like various flavours of imx or sunXi), follow the naming scheme described above. This commit ajusts ethernet aliases of Marvell Armada 38x SoC to be properly recognized by bootloaders' MAC address fixup routines. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1415980652-7429-5-git-send-email-mw@semihalf.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: remove clock-frequency from Armada 38x SDHCI Device Tree nodeMarcin Wojtas
For proper operation of Armada 38x SDHCI controller proper 'clocks' property is sufficient. Therefore it is not useful to keep an additional 'clock-frequency' property in SDHCI controller node of board-level Device Tree file for Armada 385 DB. This commit gets rid of useless 'clock-frequency' property. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1415980652-7429-4-git-send-email-mw@semihalf.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: enable no-1-8-v flag for Armada 385 DB SDHCI interfaceMarcin Wojtas
The Marvell Armada 38x SoC's SDHCI interface is capable of using 1.8v voltage, needed for driving "UHS-I" SD cards at their full speed. It is not, however, possible on the DB board. Due to physical connectivity connector supply is tied to 3v and any attempt of changing voltage in order to operate in the fastest UHS modes fails. This patch enables equivalent SDHCI quirk in order to adjust controller operation to system capabilities. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1415980652-7429-3-git-send-email-mw@semihalf.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: enable i2c device in mvebu_v7_defconfigMarcin Wojtas
This commit enables user-space access to I2C bus using char device. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1415980652-7429-6-git-send-email-mw@semihalf.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: re-enable SDHCI driver for Armada 38x SoC in v7 defconfigMarcin Wojtas
In the recent update of mvebu_v7_defconfig a config that enables sdhci-pxav3 driver, that supports SDHCI interface of Armada 38x SoC, disappeared. This commit enables CONFIG_MMC_SDHCI_PXAV3 back. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Fixes fc9fa8714a75 ("ARM: mvebu: update v7 defconfig with useful options") Link: https://lkml.kernel.org/r/1415980652-7429-2-git-send-email-mw@semihalf.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: Implement the CPU hotplug support for the Armada 38x SoCsGregory CLEMENT
This commit implements the CPU hotplug support for the Marvell Armada 38x platform. Similarly to what was done for the Armada XP, this commit: * Implements the ->cpu_die() function of SMP operations by calling armada_38x_do_cpu_suspend() to enter the deep idle state for CPUs going offline. * Implements a dummy ->cpu_kill() function, simply needed for the kernel to know we have CPU hotplug support. * The mvebu_cortex_a9_boot_secondary() function makes sure to wake up the CPU if waiting in deep idle state by sending an IPI before deasserting the CPUs from reset. This is because mvebu_cortex_a9_boot_secondary() is now used in two different situations: for the initial boot of secondary CPUs (where CPU reset deassert is used to wake up CPUs) and for CPU hotplug (where an IPI is used to take CPU out of deep idle). * At boot time, we exit from the idle state in the ->smp_secondary_init() hook. This commit has been tested using CPU hotplug through sysfs (/sys/devices/system/cpu/cpuX/online) and using kexec. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1414669184-16785-5-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: Fix the secondary startup for Cortex A9 SoCGregory CLEMENT
During the secondary startup the SCU was assumed to be in normal mode. It is not always the case, and especially after a kexec. This commit adds the needed sequence to put the SCU in normal mode. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1414669184-16785-4-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: Move SCU power up in a functionGregory CLEMENT
This will allow reusing the same function in the secondary_startup for the Cortex A9 SoC. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1414669184-16785-3-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: Clean-up the Armada XP supportGregory CLEMENT
This patch removes the unneeded include of the armada-370-xp.h header. It also moves some declarations from this file into more accurate places. Finally, it also adds a comment explaining that we can't remove yet the smp field in the dt machine struct due to backward compatibly of the device tree. In a few releases, when the old device tree will be obsolete, we will be able to remove the smp field and then the armada-370-xp.h header. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1414669184-16785-2-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: update comments in coherency.cThomas Petazzoni
The coherency.c top-level comment mentions that it supports the coherency fabric for Armada 370 and XP, but it also supports the coherency fabric on Armada 375 and 38x, so this commit updates the comment accordingly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: remove Armada 375 Z1 workaround for I/O coherencyThomas Petazzoni
This reverts commit 5ab5afd8ba83 ("ARM: mvebu: implement Armada 375 coherency workaround"), since we are removing the support for the very early Z1 revision of the Armada 375 SoC. This commit is an exact revert, with two exceptions: - minor adaptations needed due to other changes that have taken place in coherency.c since the original commit - keep the definition of pr_fmt. This shouldn't originally have been part of the Armada 375 Z1 workaround commit since it had nothing to do with it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: remove unused register offset definitionThomas Petazzoni
Since commit b21dcafea36d ("arm: mvebu: remove dependency of SMP init on static I/O mapping"), the COHERENCY_FABRIC_CFG_OFFSET register offset definition is no longer used, so this commit removes it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/375/38x/XPThomas Petazzoni
Enabling the hardware I/O coherency on Armada 370, Armada 375, Armada 38x and Armada XP requires a certain number of conditions: - On Armada 370, the cache policy must be set to write-allocate. - On Armada 375, 38x and XP, the cache policy must be set to write-allocate, the pages must be mapped with the shareable attribute, and the SMP bit must be set Currently, on Armada XP, when CONFIG_SMP is enabled, those conditions are met. However, when Armada XP is used in a !CONFIG_SMP kernel, none of these conditions are met. With Armada 370, the situation is worse: since the processor is single core, regardless of whether CONFIG_SMP or !CONFIG_SMP is used, the cache policy will be set to write-back by the kernel and not write-allocate. Since solving this problem turns out to be quite complicated, and we don't want to let users with a mainline kernel known to have infrequent but existing data corruptions, this commit proposes to simply disable hardware I/O coherency in situations where it is known not to work. And basically, the is_smp() function of the kernel tells us whether it is OK to enable hardware I/O coherency or not, so this commit slightly refactors the coherency_type() function to return COHERENCY_FABRIC_TYPE_NONE when is_smp() is false, or the appropriate type of the coherency fabric in the other case. Thanks to this, the I/O coherency fabric will no longer be used at all in !CONFIG_SMP configurations. It will continue to be used in CONFIG_SMP configurations on Armada XP, Armada 375 and Armada 38x (which are multiple cores processors), but will no longer be used on Armada 370 (which is a single core processor). In the process, it simplifies the implementation of the coherency_type() function, and adds a missing call to of_node_put(). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Fixes: e60304f8cb7bb545e79fe62d9b9762460c254ec2 ("arm: mvebu: Add hardware I/O Coherency support") Cc: <stable@vger.kernel.org> # v3.8+ Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: make the coherency_ll.S functions work with no coherency fabricThomas Petazzoni
The ll_add_cpu_to_smp_group(), ll_enable_coherency() and ll_disable_coherency() are used on Armada XP to control the coherency fabric. However, they make the assumption that the coherency fabric is always available, which is currently a correct assumption but will no longer be true with a followup commit that disables the usage of the coherency fabric when the conditions are not met to use it. Therefore, this commit modifies those functions so that they check the return value of ll_get_coherency_base(), and if the return value is 0, they simply return without configuring anything in the coherency fabric. The ll_get_coherency_base() function is also modified to properly return 0 when the function is called with the MMU disabled. In this case, it normally returns the physical address of the coherency fabric, but we now check if the virtual address is 0, and if that's case, return a physical address of 0 to indicate that the coherency fabric is not enabled. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.8+ Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22Merge branch 'mvebu/fixes' into mvebu/socJason Cooper
2014-11-21ARM: dts: cm-t3x30: add keypad supportDmitry Lifshitz
Add twl4030 matrtix keypad support. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit (git 2.34.1) at 2025-09-13 09:04:55 +0000