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2021-07-26ARM: dts: meson8b: mxq: Fix the pwm regulator supply propertiesAnand Moon
After enabling CONFIG_REGULATOR_DEBUG=y we observer below debug logs. Changes help link VCCK and VDDEE pwm regulator to 5V regulator supply instead of dummy regulator. Add missing pwm-supply for regulator-vcck regulator node. [ 7.117140] pwm-regulator regulator-vcck: Looking up pwm-supply from device tree [ 7.117153] pwm-regulator regulator-vcck: Looking up pwm-supply property in node /regulator-vcck failed [ 7.117184] VCCK: supplied by regulator-dummy [ 7.117194] regulator-dummy: could not add device link regulator.8: -ENOENT [ 7.117266] VCCK: 860 <--> 1140 mV at 986 mV, enabled [ 7.118498] VDDEE: will resolve supply early: pwm [ 7.118515] pwm-regulator regulator-vddee: Looking up pwm-supply from device tree [ 7.118526] pwm-regulator regulator-vddee: Looking up pwm-supply property in node /regulator-vddee failed [ 7.118553] VDDEE: supplied by regulator-dummy [ 7.118563] regulator-dummy: could not add device link regulator.9: -ENOENT Fixes: dee51cd0d2e8 ("ARM: dts: meson8b: mxq: add the VDDEE regulator") Fixes: d94f60e3dfa0 ("ARM: dts: meson8b: mxq: improve support for the TRONFY MXQ S805") Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210705112358.3554-3-linux.amoon@gmail.com
2021-07-26ARM: dts: meson8b: odroidc1: Fix the pwm regulator supply propertiesAnand Moon
After enabling CONFIG_REGULATOR_DEBUG=y we observe below debug logs. Changes help link VCCK and VDDEE pwm regulator to 5V regulator supply instead of dummy regulator. [ 7.117140] pwm-regulator regulator-vcck: Looking up pwm-supply from device tree [ 7.117153] pwm-regulator regulator-vcck: Looking up pwm-supply property in node /regulator-vcck failed [ 7.117184] VCCK: supplied by regulator-dummy [ 7.117194] regulator-dummy: could not add device link regulator.8: -ENOENT [ 7.117266] VCCK: 860 <--> 1140 mV at 986 mV, enabled [ 7.118498] VDDEE: will resolve supply early: pwm [ 7.118515] pwm-regulator regulator-vddee: Looking up pwm-supply from device tree [ 7.118526] pwm-regulator regulator-vddee: Looking up pwm-supply property in node /regulator-vddee failed [ 7.118553] VDDEE: supplied by regulator-dummy [ 7.118563] regulator-dummy: could not add device link regulator.9: -ENOENT Fixes: 524d96083b66 ("ARM: dts: meson8b: odroidc1: add the CPU voltage regulator") Fixes: 8bdf38be712d ("ARM: dts: meson8b: odroidc1: add the VDDEE regulator") Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [narmstrong: fixed typo in commit s/observer/observe/] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210705112358.3554-2-linux.amoon@gmail.com
2021-07-26ARM: dts: meson8b: ec100: wire up the RT5640 audio codecMartin Blumenstingl
The Realtek RT5640 codec is connected to the SoC's I2S interface. Describe this in the .dts together with the codec's LDO1 enable GPIO so audio can be played on the Endless Mini. While here, add a note about the realtek,ldo1-en-gpios for which the EC100 uses GPIO_BSD_EN. Due to driver limitations this pin cannot be used currently. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210717233030.331273-3-martin.blumenstingl@googlemail.com
2021-07-26ARM: dts: meson: Add the AIU audio controllerMartin Blumenstingl
Add the AIU audio controller to the Amlogic Meson6/8/8b/8m2 SoC DT. This provides I2S and SPDIF outputs as well as codec glues for the internal HDMI controller. Also add the clock inputs and pin mux definitions on Meson8/8b/8m2. On Meson6 this is omitted because we neither have a clock nor pin controller node there yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210717233030.331273-2-martin.blumenstingl@googlemail.com
2021-07-26ARM: multi_v7_defconfig: Enable CONFIG_MMC_MESON_MX_SDHCAnand Moon
Enable CONFIG_MMC_MESON_MX_SDHC so that SDHC host controller on Amlogic SoCs boards enable support for eMMC and MMC drivers. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210715092233.1084-1-linux.amoon@gmail.com
2021-07-26ARM: dts: meson8: Use a higher default GPU clock frequencyMartin Blumenstingl
We are seeing "imprecise external abort (0x1406)" errors during boot (which then cause the whole board to hang) on Meson8 (but not Meson8m2). These are observed while trying to access the GPU's registers when the MALI clock is running at it's default setting of 24MHz. The 3.10 vendor kernel uses 318.75MHz as "default" GPU frequency. Using that makes the "imprecise external aborts" go away. Add the assigned-clocks and assigned-clock-rates properties to also bump the MALI clock to 318.75MHz before accessing any of it's registers. Fixes: 7d3f6b536e72c9 ("ARM: dts: meson8: add the Mali-450 MP6 GPU") Reported-by: Demetris Ierokipides <ierokipides.dem@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210711214023.2163565-1-martin.blumenstingl@googlemail.com
2021-07-23signal: Verify the alignment and size of siginfo_tEric W. Biederman
Update the static assertions about siginfo_t to also describe it's alignment and size. While investigating if it was possible to add a 64bit field into siginfo_t[1] it became apparent that the alignment of siginfo_t is as much a part of the ABI as the size of the structure. If the alignment changes siginfo_t when embedded in another structure can move to a different offset. Which is not acceptable from an ABI structure. So document that fact and add static assertions to notify developers if they change change the alignment by accident. [1] https://lkml.kernel.org/r/YJEZdhe6JGFNYlum@elver.google.com Acked-by: Marco Elver <elver@google.com> v1: https://lkml.kernel.org/r/20210505141101.11519-4-ebiederm@xmission.co Link: https://lkml.kernel.org/r/875yxaxmyl.fsf_-_@disp2133 Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2021-07-23arm: Add compile-time asserts for siginfo_t offsetsMarco Elver
To help catch ABI breaks at compile-time, add compile-time assertions to verify the siginfo_t layout. This could have caught that we cannot portably add 64-bit integers to siginfo_t on 32-bit architectures like Arm before reaching -next: https://lkml.kernel.org/r/20210422191823.79012-1-elver@google.com Link: https://lkml.kernel.org/r/20210429190734.624918-2-elver@google.com Link: https://lkml.kernel.org/r/20210505141101.11519-2-ebiederm@xmission.com Link: https://lkml.kernel.org/r/87y2a7xx9q.fsf_-_@disp2133 Signed-off-by: Marco Elver <elver@google.com> Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
2021-07-23Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netDavid S. Miller
Conflicts are simple overlapping changes. Signed-off-by: David S. Miller <davem@davemloft.net>
2021-07-23ARM: dts: imx: Swap M53Menlo pinctrl_power_button/pinctrl_power_out pinsMarek Vasut
The pinctrl_power_button/pinctrl_power_out each define single GPIO pinmux, except it is exactly the other one than the matching gpio-keys and gpio-poweroff DT nodes use for that functionality. Swap the two GPIOs to correct this error. Fixes: 50d29fdb765d ("ARM: dts: imx53: Add power GPIOs on M53Menlo") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: imx: fix missing 3rd argument in macro imx_mmdc_perf_initColin Ian King
The function imx_mmdc_perf_init recently had a 3rd argument added to it but the equivalent macro was not updated and is still the older 2 argument version. Fix this by adding in the missing 3rd argumement mmdc_ipg_clk. Fixes: f07ec8536580 ("ARM: imx: add missing clk_disable_unprepare()") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx6q-dhcom: Set minimum memory size of all DHCOM i.MX6 variantsChristoph Niedermaier
The minimum available memory size of all DHCOM i.MX6 variants is 512 MB. Set this value for the memory node. If U-Boot fails to fill the memory size, at least all DHCOM i.MX6 variants should run without problems. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx6q-dhcom: Remove ddc-i2c-bus propertyChristoph Niedermaier
An EDID lookup is not needed with this panel. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx6q-dhcom: Add keys and leds to the PDK2 boardChristoph Niedermaier
On the PDK2 there are 4 keys and 4 leds. DHCOM GPIOs are used for that, but one led isn't useable, because the GPIO is already used as touch interrupt. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx6q-dhcom: Align stdout-path with other DHCOM SoMsChristoph Niedermaier
Set stdout-path to "serial0:15200n8" to align it with other DHCOM SoMs like the DHCOM STM32MP1. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrlChristoph Niedermaier
The pin CSI0_DATA_EN is reserved for PCIe Wake. Move this pin to the SoM devicetree. Add PCIe Reset GPIO to the board devicetree. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx6q-dhcom: Fill GPIO line names on DHCOM SoMChristoph Niedermaier
Fill in the custom GPIO line names used by DH on the DHCOM SoM. The GPIO line names are in accordance to DHCOM Design Guide R04 available at [1], section 3.9 GPIO. Adding also GPIO line names for the hardware and memory coding. [1] https://wiki.dh-electronics.com/images/5/52/DOC_DHCOM-Design-Guide_R04_2018-06-28.pdf Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx6q-dhcom: Add interrupt and compatible to the ethernet PHYChristoph Niedermaier
Enable the interrupt mode for the ethernet PHY by adding the necessary property and a separate pinctrl for the PHY. Also add the compatible property for it. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx6q-dhcom: Add the parallel system busChristoph Niedermaier
Add the parallel system bus provided by the i.MX6 WEIM interface via an address latch. The OE pin of the latch is controlled by a fixed regulator. The pin is low active. This is ensured by omitting the regulators property enable-active-high. The flags value of the gpio property (3rd value), which is also use to define active high/low, is set to 0 because it is ignored by gpiolib-of.c. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23Revert "ARM: dts: imx6: Use correct SDMA script for SPI cores"Robin Gong
There are two ways for SDMA accessing SPBA devices: one is SDMA->AIPS ->SPBA(masterA port), another is SDMA->SPBA(masterC port). Please refer to the 'Figure 58-1. i.MX 6Dual/6Quad SPBA connectivity' of i.mx6DQ Reference Manual. SDMA provide the corresponding app_2_mcu/mcu_2_app and shp_2_mcu/mcu_2_shp script for such two options. So both AIPS and SPBA scripts should keep the same behaviour, the issue only caught in AIPS script sounds not solide. The issue is more likely as the ecspi errata ERR009165(http://www.nxp.com/docs/en/errata/IMX6DQCE.pdf): eCSPI: TXFIFO empty flag glitch can cause the current FIFO transfer to be sent twice So revert commit 'dd4b487b32a3' firstly. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23Revert "ARM: dts: imx6q: Use correct SDMA script for SPI5 core"Robin Gong
There are two ways for SDMA accessing SPBA devices: one is SDMA->AIPS ->SPBA(masterA port), another is SDMA->SPBA(masterC port). Please refer to the 'Figure 58-1. i.MX 6Dual/6Quad SPBA connectivity' of i.mx6DQ Reference Manual. SDMA provide the corresponding app_2_mcu/mcu_2_app and shp_2_mcu/mcu_2_shp script for such two options. So both AIPS and SPBA scripts should keep the same behaviour, the issue only caught in AIPS script sounds not solide. The issue is more likely as the ecspi errata ERR009165(http://www.nxp.com/docs/en/errata/IMX6DQCE.pdf): eCSPI: TXFIFO empty flag glitch can cause the current FIFO transfer to be sent twice So revert commit 'df07101e1c4a' firstly. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: colibri-imx6ull: limit SDIO clock to 25MHzOleksandr Suvorov
NXP and AzureWave don't recommend using SDIO bus mode 3.3V@50MHz due to noise affecting the wireless throughput. Colibri iMX6ULL uses only 3.3V signaling for Wi-Fi module AW-CM276NF. Limit the SDIO Clock on Colibri iMX6ULL to 25MHz. Fixes: c2e4987e0e02 ("ARM: dts: imx6ull: add Toradex Colibri iMX6ULL support") Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx7d-remarkable2: Add WiFi supportAlistair Francis
Add support for the bcm4329-fmac WiFi in the reMarkable 2, connected via SDHC. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx6qdl-gw5904: atecc508a supportTim Harvey
Add one node for the Atmel ATECC508A 'CryptoAuthentication' i2c device. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23ARM: dts: imx6qdl-gw5xxx: add missing USB OTG OC pinmuxTim Harvey
Add USB OTG over-current pinmux to the GW51xx/GW52xx/GW54xx/GW553x boards. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-07-23Merge tag 'drm-misc-next-2021-07-22' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.15-rc1: UAPI Changes: - Remove sysfs stats for dma-buf attachments, as it causes a performance regression. Previous merge is not in a rc kernel yet, so no userspace regression possible. Cross-subsystem Changes: - Sanitize user input in kyro's viewport ioctl. - Use refcount_t in fb_info->count - Assorted fixes to dma-buf. - Extend x86 efifb handling to all archs. - Fix neofb divide by 0. - Document corpro,gm7123 bridge dt bindings. Core Changes: - Slightly rework drm master handling. - Cleanup vgaarb handling. - Assorted fixes. Driver Changes: - Add support for ws2401 panel. - Assorted fixes to stm, ast, bochs. - Demidlayer ingenic irq. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2d0d2fe8-01fc-e216-c3fd-38db9e69944e@linux.intel.com
2021-07-21ARM: dts: imx6qdl: move phy properties into phy device nodeJoakim Zhang
This patch fixes issues found by dtbs_check: make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/fsl,fec.yaml According to the Micrel PHY dt-binding: Documentation/devicetree/bindings/net/micrel-ksz90x1.txt, Add clock delay in an Ethernet OF device node is deprecated, so move these properties to PHY OF device node. Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-07-21drivers/firmware: consolidate EFI framebuffer setup for all archesJavier Martinez Canillas
The register_gop_device() function registers an "efi-framebuffer" platform device to match against the efifb driver, to have an early framebuffer for EFI platforms. But there is already support to do exactly the same by the Generic System Framebuffers (sysfb) driver. This used to be only for X86 but it has been moved to drivers/firmware and could be reused by other architectures. Also, besides supporting registering an "efi-framebuffer", this driver can register a "simple-framebuffer" allowing to use the siple{fb,drm} drivers on non-X86 EFI platforms. For example, on aarch64 these drivers can only be used with DT and doesn't have code to register a "simple-frambuffer" platform device when booting with EFI. For these reasons, let's remove the register_gop_device() duplicated code and instead move the platform specific logic that's there to sysfb driver. Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Acked-by: Borislav Petkov <bp@suse.de> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210625131359.1804394-1-javierm@redhat.com
2021-07-21bus: Make remove callback return voidUwe Kleine-König
The driver core ignores the return value of this callback because there is only little it can do when a device disappears. This is the final bit of a long lasting cleanup quest where several buses were converted to also return void from their remove callback. Additionally some resource leaks were fixed that were caused by drivers returning an error code in the expectation that the driver won't go away. With struct bus_type::remove returning void it's prevented that newly implemented buses return an ignored error code and so don't anticipate wrong expectations for driver authors. Reviewed-by: Tom Rix <trix@redhat.com> (For fpga) Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> (For drivers/s390 and drivers/vfio) Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> (For ARM, Amba and related parts) Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> (for sunxi-rsb) Acked-by: Pali Rohár <pali@kernel.org> Acked-by: Mauro Carvalho Chehab <mchehab@kernel.org> (for media) Acked-by: Hans de Goede <hdegoede@redhat.com> (For drivers/platform) Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-By: Vinod Koul <vkoul@kernel.org> Acked-by: Juergen Gross <jgross@suse.com> (For xen) Acked-by: Lee Jones <lee.jones@linaro.org> (For mfd) Acked-by: Johannes Thumshirn <jth@kernel.org> (For mcb) Acked-by: Johan Hovold <johan@kernel.org> Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> (For slimbus) Acked-by: Kirti Wankhede <kwankhede@nvidia.com> (For vfio) Acked-by: Maximilian Luz <luzmaximilian@gmail.com> Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> (For ulpi and typec) Acked-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> (For ipack) Acked-by: Geoff Levand <geoff@infradead.org> (For ps3) Acked-by: Yehezkel Bernat <YehezkelShB@gmail.com> (For thunderbolt) Acked-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> (For intel_th) Acked-by: Dominik Brodowski <linux@dominikbrodowski.net> (For pcmcia) Acked-by: Rafael J. Wysocki <rafael@kernel.org> (For ACPI) Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> (rpmsg and apr) Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> (For intel-ish-hid) Acked-by: Dan Williams <dan.j.williams@intel.com> (For CXL, DAX, and NVDIMM) Acked-by: William Breathitt Gray <vilhelm.gray@gmail.com> (For isa) Acked-by: Stefan Richter <stefanr@s5r6.in-berlin.de> (For firewire) Acked-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> (For hid) Acked-by: Thorsten Scherer <t.scherer@eckelmann.de> (For siox) Acked-by: Sven Van Asbroeck <TheSven73@gmail.com> (For anybuss) Acked-by: Ulf Hansson <ulf.hansson@linaro.org> (For MMC) Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Finn Thain <fthain@linux-m68k.org> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20210713193522.1770306-6-u.kleine-koenig@pengutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-07-19ARM: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo phoneBartosz Dudziak
Add DTS support for the Samsung Galaxy S III Neo (codenamed s3ve3g) phone. Initial version have just a working serial console. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210418122909.71434-6-bartosz.dudziak@snejp.pl Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-07-19ARM: dts: qcom: Add support for MSM8226 SoCBartosz Dudziak
Implement basic device tree support for MSM8226 SoC which belongs to the Snapdragon 400 family. For now, this file adds the basic nodes like gcc, pinctrl and other required configuration for booting up to the serial console. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210418122909.71434-4-bartosz.dudziak@snejp.pl Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-07-19ARM: dts: qcom: apq8060: Correct Ethernet node name and drop bogus irq propertyGeert Uytterhoeven
make dtbs_check: ethernet-ebi2@2,0: $nodename:0: 'ethernet-ebi2@2,0' does not match '^ethernet(@.*)?$' ethernet-ebi2@2,0: 'smsc,irq-active-low' does not match any of the regexes: 'pinctrl-[0-9]+' There is no "smsc,irq-active-low" property, as active low is the default. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/d58c8323c3d544f91f7e4585a5b163bc374397d1.1625140615.git.geert+renesas@glider.be Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-07-19ARM: dts: qcom: apq8064: correct clock namesDavid Heidelberg
Since new code doesn't take old clk names in account, it does fixes error: msm_dsi 4700000.mdss_dsi: dev_pm_opp_set_clkname: Couldn't find clock: -2 and following kernel oops introduced by b0530eb1191 ("drm/msm/dpu: Use OPP API to set clk/perf state"). Also removes warning about deprecated clock names. Tested against linux-5.10.y LTS on Nexus 7 2013. Reviewed-by: Brian Masney <masneyb@onstation.org> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20210707131453.24041-1-david@ixit.cz Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-07-19ARM: dts: qcom: msm8974-klte: Enable remote processorsAlexey Minnekhanov
Override power supplies to proper ones, thus enabling to power on ADSP and modem remoteprocs. Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org> Link: https://lore.kernel.org/r/20210710085509.105320-1-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-07-19ARM: dts: at91: sama5d4_xplained: Remove spi0 nodeTudor Ambarus
sama5d4_xplained has an optional on-board serial DataFlash (AT25DF321A), which does not come populated on board by default. Since the spi0 node does not have any child populated by default, thus no user on sama5d4_xplained, remove it. This avoids the following error in SPI NOR, which reads the values of the pulled downed lines, unrecognizing the flash: spi-nor spi0.0: unrecognized JEDEC id bytes: 00 00 00 00 00 00 Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210716154739.835738-1-tudor.ambarus@microchip.com
2021-07-19ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ekEugen Hristev
Add Device Tree for sama7g5 SoC and associated board sama7g5-ek Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea@microchip.com: add clocks, ethernet, timers, power] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> [codrin.ciubotariu@microchip.com: add audio] Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> [nicolas.ferre@microchip.com: removed eeproms, reorder i2s dma chans] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210628120452.74408-2-eugen.hristev@microchip.com
2021-07-19ARM: multi_v7_defconfig: add sama7g5 SoCEugen Hristev
Add the Microchip SAMA7G5 ARM v7 Cortex-A7 based SoC to multi_v7_defconfig. Also add it's clock timer, the PIT64B. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210628120452.74408-4-eugen.hristev@microchip.com
2021-07-19ARM: configs: at91: add defconfig for sama7 family of SoCsEugen Hristev
Add defconfig for sama7 SoC family. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea@microchip.com: add clocks, ethernet, timers, power] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> [codrin.ciubotariu@microchip.com: add audio] Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> [nicolas.ferre@microchip.com: atags not set, mtd tests, spi gpio] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210628120452.74408-3-eugen.hristev@microchip.com
2021-07-19ARM: at91: pm: add sama7g5 shdwcClaudiu Beznea
Add SAMA7G5 SHDWC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-25-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add pm support for SAMA7G5Claudiu Beznea
Add support for SAMA7G5 power management modes: standby, ulp0, ulp1, backup. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-24-claudiu.beznea@microchip.com
2021-07-19ARM: at91: sama7: introduce sama7 SoC familyEugen Hristev
Introduce new family of SoCs, sama7, and first SoC, sama7g5. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea@microchip.com: keep only the sama7_dt] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-23-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add sama7g5's pmcClaudiu Beznea
Add SAMA7G5's PMC to compatible list. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-22-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add backup mode support for SAMA7G5Claudiu Beznea
Adapt at91_pm_backup_init() to work for SAMA7G5. Also, set the LPM pin to shutdown controller. This will signal to PMIC that it needs to switch to the state corresponding to backup mode. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-21-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: save ddr phy calibration data to securamClaudiu Beznea
The resuming from backup mode is done with the help of bootloader. The bootloader reconfigure the DDR controller and DDR PHY controller. To speed-up the resuming process save the PHY calibration data into SECURAM before suspending (securam is powered on backup mode). This data will be later used by bootloader in DDR PHY reconfiguration process. Also, in the process or recalibration the first 8 words of the memory may get corrupted. To solve this, these 8 words are saved in the securam and restored by bootloader in the process of PHY configuration. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-20-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add sama7g5 ddr phy controllerClaudiu Beznea
SAMA7G5 self-refresh procedure accesses also the DDR PHY registers. Adapt the code so that the at91_dt_ramc() to look also for DDR PHYs, in case it is mandatory. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-19-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add sama7g5 ddr controllerClaudiu Beznea
Add SAMA7G5 DDR controller to the list of DDR controller compatibles. At the moment there is no standby support. Adapt the code for this. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: wait for ddr power mode offClaudiu Beznea
Wait for DDR power mode off before shutting down the core. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-16-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add support for 2.5V LDO regulator controlClaudiu Beznea
Add support to disable/enable 2.5V LDO regulator when entering/exiting any ULP mode. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-15-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add support for MCK1..4 save/restore for ulp modesClaudiu Beznea
Add support for MCK1..4 save restore for ULP modes. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-14-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add self-refresh support for sama7g5Claudiu Beznea
Add self-refresh support for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-13-claudiu.beznea@microchip.com